baseband/fpga_5gnr_fec: add PMD for FPGA 5GNR FEC
Add stubs for the FPGA 5GNR FEC PMD Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Niall Power <niall.power@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
db06104c30
commit
0b5927cbcb
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@ -576,6 +576,11 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y
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#
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CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC=y
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#
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# Compile PMD for Intel FPGA 5GNR FEC bbdev device
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#
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CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC=y
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#
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# Compile generic crypto device library
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#
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146
doc/guides/bbdevs/fpga_5gnr_fec.rst
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146
doc/guides/bbdevs/fpga_5gnr_fec.rst
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@ -0,0 +1,146 @@
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.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2019 Intel Corporation
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Intel(R) FPGA 5GNR FEC Poll Mode Driver
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=======================================
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The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
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LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
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based Vista Creek device.
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Features
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--------
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FPGA 5GNR FEC PMD supports the following features:
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- 8 VFs per PF (physical device)
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- Maximum of 32 UL queues per VF
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- Maximum of 32 DL queues per VF
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- PCIe Gen-3 x8 Interface
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- MSI-X
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- SR-IOV
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Limitations
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-----------
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FPGA 5GNR FEC does not support the following:
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- Scatter-Gather function
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Installation
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------------
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Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The
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default set of bbdev compile flags may be found in config/common_base, where for example
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the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
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is already set. It is assumed DPDK has been compiled using for instance:
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.. code-block:: console
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make install T=x86_64-native-linuxapp-gcc
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DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
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The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
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hugepage configuration of a server may be examined using:
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.. code-block:: console
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grep Huge* /proc/meminfo
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Initialization
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--------------
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When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
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.. code-block:: console
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sudo lspci -vd8086:0d8f
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The physical and virtual functions are compatible with Linux UIO drivers:
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``vfio`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
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to be bound to one of these linux drivers through DPDK.
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Bind PF UIO driver(s)
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~~~~~~~~~~~~~~~~~~~~~
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Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
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``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
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The igb_uio driver may be bound to the PF PCI device using one of three methods:
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1. PCI functions (physical or virtual, depending on the use case) can be bound to
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the UIO driver by repeating this command for every function.
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.. code-block:: console
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cd <dpdk-top-level-directory>
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insmod ./build/kmod/igb_uio.ko
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echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
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lspci -vd8086:0d8f
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2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
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.. code-block:: console
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cd <dpdk-top-level-directory>
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./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
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where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f
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3. A third way to bind is to use ``dpdk-setup.sh`` tool
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.. code-block:: console
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cd <dpdk-top-level-directory>
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./usertools/dpdk-setup.sh
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select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
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or
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select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
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enter PCI device ID
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select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
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In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not
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support SR-IOV configuration right out of the box, so it will need to be patched.
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Enable Virtual Functions
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~~~~~~~~~~~~~~~~~~~~~~~~
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Now, it should be visible in the printouts that PCI PF is under igb_uio control
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"``Kernel driver in use: igb_uio``"
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To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
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.. code-block:: console
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cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
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where 0000\:<b>\:<d>.<f> is the PCI device ID
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To enable VFs via igb_uio, echo the number of virtual functions intended to
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enable to ``max_vfs`` file..
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.. code-block:: console
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echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
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Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
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way it was done with the physical function previously.
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Enabling SR-IOV via vfio driver is pretty much the same, except that the file
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name is different:
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.. code-block:: console
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echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
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@ -11,3 +11,4 @@ Baseband Device Drivers
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null
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turbo_sw
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fpga_lte_fec
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fpga_5gnr_fec
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@ -104,6 +104,12 @@ New Features
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Supported large size code blocks which does not fit in one mbuf segment.
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* **Added Intel FPGA_5GNR_FEC bbdev PMD.**
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Added a new ``fpga_5gnr_fec`` bbdev driver for the Intel\ |reg| FPGA PAC
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(Programmable Acceleration Card) N3000. See the
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:doc:`../bbdevs/fpga_5gnr_fec` BBDEV guide for more details on this new driver.
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* **Updated ipsec-secgw sample application with following features.**
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* Updated ipsec-secgw application to add event based packet processing.
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@ -12,5 +12,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += turbo_sw
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DEPDIRS-turbo_sw = $(core-libs)
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DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_lte_fec
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DEPDIRS-fpga_lte_fec = $(core-libs)
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DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += fpga_5gnr_fec
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DEPDIRS-fpga_5gnr_fec = $(core-libs)
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include $(RTE_SDK)/mk/rte.subdir.mk
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25
drivers/baseband/fpga_5gnr_fec/Makefile
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25
drivers/baseband/fpga_5gnr_fec/Makefile
Normal file
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@ -0,0 +1,25 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2019 Intel Corporation
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include $(RTE_SDK)/mk/rte.vars.mk
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# library name
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LIB = librte_pmd_bbdev_fpga_5gnr_fec.a
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# build flags
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CFLAGS += -O3
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CFLAGS += $(WERROR_FLAGS)
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LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
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LDLIBS += -lrte_bbdev
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LDLIBS += -lrte_pci -lrte_bus_pci
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# versioning export map
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EXPORT_MAP := rte_pmd_bbdev_fpga_5gnr_fec_version.map
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# library version
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LIBABIVER := 1
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# library source files
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SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += rte_fpga_5gnr_fec.c
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include $(RTE_SDK)/mk/rte.lib.mk
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41
drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
Normal file
41
drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
Normal file
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Intel Corporation
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*/
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#ifndef _FPGA_5GNR_FEC_H_
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#define _FPGA_5GNR_FEC_H_
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#include <stdint.h>
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#include <stdbool.h>
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \
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##__VA_ARGS__)
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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#define rte_bbdev_log_debug(fmt, ...) \
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rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \
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##__VA_ARGS__)
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#else
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#define rte_bbdev_log_debug(fmt, ...)
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#endif
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/* FPGA 5GNR FEC driver names */
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#define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf
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#define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf
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/* FPGA 5GNR FEC PCI vendor & device IDs */
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#define FPGA_5GNR_FEC_VENDOR_ID (0x8086)
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#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)
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#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)
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/* Private data structure for each FPGA FEC device */
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struct fpga_5gnr_fec_device {
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/** Base address of MMIO registers (BAR0) */
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void *mmio_base;
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/** True if this is a PF FPGA FEC device */
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bool pf_device;
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};
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#endif /* _FPGA_5GNR_FEC_H_ */
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6
drivers/baseband/fpga_5gnr_fec/meson.build
Normal file
6
drivers/baseband/fpga_5gnr_fec/meson.build
Normal file
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2020 Intel Corporation
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deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
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sources = files('rte_fpga_5gnr_fec.c')
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193
drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
Normal file
193
drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
Normal file
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@ -0,0 +1,193 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Intel Corporation
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*/
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#include <unistd.h>
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#include <rte_common.h>
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#include <rte_log.h>
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#include <rte_dev.h>
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#include <rte_malloc.h>
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#include <rte_mempool.h>
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#include <rte_errno.h>
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#include <rte_pci.h>
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#include <rte_bus_pci.h>
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#include <rte_byteorder.h>
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#include <rte_bbdev.h>
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#include <rte_bbdev_pmd.h>
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#include "fpga_5gnr_fec.h"
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/* 5GNR SW PMD logging ID */
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static int fpga_5gnr_fec_logtype;
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static int
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fpga_dev_close(struct rte_bbdev *dev __rte_unused)
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{
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return 0;
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}
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static const struct rte_bbdev_ops fpga_ops = {
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.close = fpga_dev_close,
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};
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/* Initialization Function */
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static void
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fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
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{
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struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
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dev->dev_ops = &fpga_ops;
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((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =
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!strcmp(drv->driver.name,
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RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));
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((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =
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pci_dev->mem_resource[0].addr;
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rte_bbdev_log_debug(
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"Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
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dev->device->driver->name, dev->data->name,
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(void *)pci_dev->mem_resource[0].addr,
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pci_dev->mem_resource[0].phys_addr);
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}
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static int
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fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,
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struct rte_pci_device *pci_dev)
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{
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struct rte_bbdev *bbdev = NULL;
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char dev_name[RTE_BBDEV_NAME_MAX_LEN];
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if (pci_dev == NULL) {
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rte_bbdev_log(ERR, "NULL PCI device");
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return -EINVAL;
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}
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rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
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/* Allocate memory to be used privately by drivers */
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bbdev = rte_bbdev_allocate(pci_dev->device.name);
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if (bbdev == NULL)
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return -ENODEV;
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/* allocate device private memory */
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bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
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sizeof(struct fpga_5gnr_fec_device),
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RTE_CACHE_LINE_SIZE,
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pci_dev->device.numa_node);
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if (bbdev->data->dev_private == NULL) {
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rte_bbdev_log(CRIT,
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"Allocate of %zu bytes for device \"%s\" failed",
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sizeof(struct fpga_5gnr_fec_device), dev_name);
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rte_bbdev_release(bbdev);
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return -ENOMEM;
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}
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/* Fill HW specific part of device structure */
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bbdev->device = &pci_dev->device;
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bbdev->intr_handle = &pci_dev->intr_handle;
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bbdev->data->socket_id = pci_dev->device.numa_node;
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/* Invoke FEC FPGA device initialization function */
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fpga_5gnr_fec_init(bbdev, pci_drv);
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rte_bbdev_log_debug("bbdev id = %u [%s]",
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bbdev->data->dev_id, dev_name);
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return 0;
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}
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static int
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fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)
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{
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struct rte_bbdev *bbdev;
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int ret;
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uint8_t dev_id;
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if (pci_dev == NULL)
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return -EINVAL;
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/* Find device */
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bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
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if (bbdev == NULL) {
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rte_bbdev_log(CRIT,
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"Couldn't find HW dev \"%s\" to uninitialise it",
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pci_dev->device.name);
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return -ENODEV;
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}
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dev_id = bbdev->data->dev_id;
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/* free device private memory before close */
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rte_free(bbdev->data->dev_private);
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/* Close device */
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ret = rte_bbdev_close(dev_id);
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if (ret < 0)
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rte_bbdev_log(ERR,
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"Device %i failed to close during uninit: %i",
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dev_id, ret);
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/* release bbdev from library */
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ret = rte_bbdev_release(bbdev);
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if (ret)
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rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
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ret);
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rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
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return 0;
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}
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/* FPGA 5GNR FEC PCI PF address map */
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static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {
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{
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RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
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FPGA_5GNR_FEC_PF_DEVICE_ID)
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},
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{.device_id = 0},
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};
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static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {
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.probe = fpga_5gnr_fec_probe,
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.remove = fpga_5gnr_fec_remove,
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.id_table = pci_id_fpga_5gnr_fec_pf_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING
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};
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/* FPGA 5GNR FEC PCI VF address map */
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static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {
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{
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RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
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FPGA_5GNR_FEC_VF_DEVICE_ID)
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},
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{.device_id = 0},
|
||||
};
|
||||
|
||||
static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {
|
||||
.probe = fpga_5gnr_fec_probe,
|
||||
.remove = fpga_5gnr_fec_remove,
|
||||
.id_table = pci_id_fpga_5gnr_fec_vf_map,
|
||||
.drv_flags = RTE_PCI_DRV_NEED_MAPPING
|
||||
};
|
||||
|
||||
|
||||
RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);
|
||||
RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,
|
||||
pci_id_fpga_5gnr_fec_pf_map);
|
||||
RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);
|
||||
RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,
|
||||
pci_id_fpga_5gnr_fec_vf_map);
|
||||
|
||||
RTE_INIT(fpga_5gnr_fec_init_log)
|
||||
{
|
||||
fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec");
|
||||
if (fpga_5gnr_fec_logtype >= 0)
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG);
|
||||
#else
|
||||
rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
DPDK_20.0 {
|
||||
local: *;
|
||||
};
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright(c) 2018 Luca Boccassi <bluca@debian.org>
|
||||
|
||||
drivers = ['null', 'turbo_sw', 'fpga_lte_fec']
|
||||
drivers = ['null', 'turbo_sw', 'fpga_lte_fec', 'fpga_5gnr_fec']
|
||||
|
||||
config_flag_fmt = 'RTE_LIBRTE_PMD_BBDEV_@0@'
|
||||
driver_name_fmt = 'rte_pmd_bbdev_@0@'
|
||||
|
|
|
|||
|
|
@ -246,6 +246,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_NETVSC_PMD) += -lrte_pmd_netvsc
|
|||
ifeq ($(CONFIG_RTE_LIBRTE_BBDEV),y)
|
||||
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL) += -lrte_pmd_bbdev_null
|
||||
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += -lrte_pmd_bbdev_fpga_lte_fec
|
||||
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += -lrte_pmd_bbdev_fpga_5gnr_fec
|
||||
|
||||
# TURBO SOFTWARE PMD is dependent on the FLEXRAN library
|
||||
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw
|
||||
|
|
|
|||
Loading…
Reference in a new issue