9311beeea4
New cn98xx SOC comes up with two NIX blocks wrt cn96xx, cn93xx, to achieve higher performance. Also the no of cores increased to 36 from 24. Adding support for cn98xx where need a logic to detect if the LF is attached to NIX0 or NIX1 and then accordingly use the respective NIX block. Signed-off-by: Harman Kalra <hkalra@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
19 lines
400 B
Plaintext
19 lines
400 B
Plaintext
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2018 Marvell International Ltd
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#
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#include "defconfig_arm64-armv8a-linux-gcc"
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CONFIG_RTE_MACHINE="octeontx2"
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CONFIG_RTE_MAX_NUMA_NODES=1
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CONFIG_RTE_MAX_LCORE=36
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CONFIG_RTE_ARM_FEATURE_ATOMICS=y
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# Doesn't support NUMA
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CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
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CONFIG_RTE_LIBRTE_VHOST_NUMA=n
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# Max supported NIX LFs
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CONFIG_RTE_MAX_VFIO_GROUPS=128
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