642 lines
19 KiB
C
642 lines
19 KiB
C
/*****************************************************************************
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* File: fm10k.c
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* Creation Date: December 20, 2020
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*
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* Copyright (c) 2014 - 2015, Intel Corporation
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* Copyright (c) 2021, FM10K-Documentation Contributors
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the copyright holders nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#include "fm10k.h"
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#include <stdio.h>
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#include <dirent.h>
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#include <limits.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <time.h>
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#include <sys/mman.h>
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#include <fcntl.h>
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KNOWN_FLASH_DEVICE KNOWN_FLASH_DEVICE_LIST[] = {
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{{0x0101271f}, "Adesto AT45DB321E 32-Mbit", 32}, // Present on Silicom PE3100G2DQiRM-QX4
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{{0x001540ef}, "Winbond W25Q16JV 16-Mbit", 16}, // Present on Intel FM10420-100GbE-QDA2
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{{0}, "", 0}
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};
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void ReadRegister32(uintptr_t mem, uint32_t addr, uint32_t *value) {
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*value = *(((volatile uint32_t *) mem) + addr);
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}
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void WriteRegister32(uintptr_t mem, uint32_t addr, uint32_t value) {
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*(((volatile uint32_t *) mem) + addr) = value;
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//If returning instantly this will caused missed writes. nanosleep wait of 1 nsec was too much. Busy wait works
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wunused-but-set-variable"
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volatile uint32_t dummy;
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for (uint32_t i = 0; i < 100; ++i) {
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dummy = i;
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}
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#pragma GCC diagnostic pop
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}
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uint32_t get_interval_diff(struct timeval *begin, struct timeval *end) {
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struct timeval endT;
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struct timeval diff;
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if (end == NULL) {
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gettimeofday(&endT, NULL);
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} else {
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endT.tv_sec = end->tv_sec;
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endT.tv_usec = end->tv_usec;
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}
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diff.tv_sec = endT.tv_sec - begin->tv_sec;
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diff.tv_usec = endT.tv_usec - begin->tv_usec;
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return (diff.tv_sec * 1000 + diff.tv_usec / 1000);
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}
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uint32_t fm10k_mem_spi_SetCtrlReg(uintptr_t mem, SPI_CTRL value) {
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struct timeval startTime;
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uint8_t isTimeout = 0;
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SPI_CTRL spiCtrl = {0};
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WriteRegister32(mem, FM10K_REGISTER_SPI_CTRL, value.value);
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gettimeofday(&startTime, NULL);
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do {
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if (isTimeout) {
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printf("Timeout waiting for SPI_CTRL.Busy 0x%02x\n", spiCtrl.value);
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return 1;
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}
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if (get_interval_diff(&startTime, NULL) > 50) {
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isTimeout = 1;
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}
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, &spiCtrl.value);
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} while (spiCtrl.fields.Busy);
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/* write back SPI_CTRL with command = 0 */
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spiCtrl.fields.Command = 0;
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WriteRegister32(mem, FM10K_REGISTER_SPI_CTRL, spiCtrl.value);
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return 0;
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}
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void fm10k_mem_spi_Enable(uintptr_t mem) {
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//ENABLE SPI
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SPI_CTRL spiCtrl;
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, &spiCtrl.value);
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/* keep current freq setting and set SPI Enable */
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SPI_CTRL newSpiCtrl;
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newSpiCtrl.value = 0;
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newSpiCtrl.fields.Freq = spiCtrl.fields.Freq;
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newSpiCtrl.fields.Enable = 1;
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WriteRegister32(mem, FM10K_REGISTER_SPI_CTRL, newSpiCtrl.value);
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}
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void fm10k_mem_spi_Disable(uintptr_t mem) {
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//DISABLE SPI
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SPI_CTRL spiCtrl;
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, &spiCtrl.value);
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/* keep current freq setting and set SPI Enable = 0 */
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SPI_CTRL newSpiCtrl;
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newSpiCtrl.value = 0;
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newSpiCtrl.fields.Freq = spiCtrl.fields.Freq;
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WriteRegister32(mem, FM10K_REGISTER_SPI_CTRL, newSpiCtrl.value);
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}
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//Error if result.value is 0x00
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SPI_COMMAND_READ_MANUFACTURER_RESULT fm10k_mem_spi_ReadManufacturerData(uintptr_t mem) {
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SPI_COMMAND_READ_MANUFACTURER_RESULT result = {0};
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SPI_CTRL currentSpiCtrl;
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SPI_CTRL spiCtrl = {0};
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uint32_t header;
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int32_t freq;
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fm10k_mem_spi_Enable(mem);
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, ¤tSpiCtrl.value);
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if (FM10K_SPI_FREQ_KHZ > 0) {
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freq = ((100000 / (int) FM10K_SPI_FREQ_KHZ) / 2) - 1;
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if (freq < 0) {
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freq = 0;
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}
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spiCtrl.fields.Freq = freq;
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}
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spiCtrl.fields.Enable = currentSpiCtrl.fields.Enable;
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/* header: command (1 byte: READ_BYTES) */
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header = FM10K_SPI_HEADER_COMMAND_READ_MANUFACTURER_INFORMATION;
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WriteRegister32(mem, FM10K_REGISTER_SPI_HEADER, header);
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/* first loop only: set send header flag. Following loops: shift only data. */
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spiCtrl.fields.Command |= 0x1;
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spiCtrl.fields.Command |= 0x4;
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spiCtrl.fields.HeaderSize = 1;
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spiCtrl.fields.DataSize = 0x4 & 3;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return result;
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}
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uint32_t rxData;
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/* get data */
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ReadRegister32(mem, FM10K_REGISTER_SPI_RX_DATA, &rxData);
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result.value = ((rxData >> 24) & 0xff) | ((rxData << 8) & 0xff0000) | ((rxData >> 8) & 0xff00) |
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((rxData << 24) & 0xff000000);
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/* release CS */
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spiCtrl.fields.Command = 0x8;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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result.value = 0;
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return result;
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}
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fm10k_mem_spi_Disable(mem);
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return result;
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}
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uint32_t fm10k_mem_spi_ReadFlash(uintptr_t mem, uint32_t address, uint8_t *data, uint32_t len) {
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SPI_CTRL currentSpiCtrl;
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SPI_CTRL spiCtrl = {0};
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uint32_t rxData;
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uint32_t header;
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int32_t freq;
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uint32_t cnt;
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uint32_t numRead;
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fm10k_mem_spi_Enable(mem);
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, ¤tSpiCtrl.value);
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if (FM10K_SPI_FREQ_KHZ > 0) {
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freq = ((100000 / (int) FM10K_SPI_FREQ_KHZ) / 2) - 1;
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if (freq < 0) {
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freq = 0;
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}
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spiCtrl.fields.Freq = freq;
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}
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spiCtrl.fields.Enable = currentSpiCtrl.fields.Enable;
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/* header: command (1 byte: READ_BYTES) + address (3 bytes) */
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header = (FM10K_SPI_HEADER_COMMAND_READ_BYTES << 24) | (address & 0xffffff);
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WriteRegister32(mem, FM10K_REGISTER_SPI_HEADER, header);
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/* first loop only: set send header flag. Following loops: shift only data. */
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spiCtrl.fields.Command |= 0x1;
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cnt = 0;
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while (cnt < len) {
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/* determine the number of data bytes to read [1..4] */
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numRead = (len - cnt) > 3 ? 4 : (len - cnt);
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/* set 'shift data' flag and number of data bytes */
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spiCtrl.fields.Command |= 0x4;
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spiCtrl.fields.DataSize = numRead & 3;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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/* get data */
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ReadRegister32(mem, FM10K_REGISTER_SPI_RX_DATA, &rxData);
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/* push the read data into the array */
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while (numRead) {
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numRead--;
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data[cnt++] = (rxData >> (numRead * 8)) & 0xff;
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}
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spiCtrl.fields.Command = 0;
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spiCtrl.fields.DataSize = 0;
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}
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/* release CS */
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spiCtrl.fields.Command = 0x8;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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fm10k_mem_spi_Disable(mem);
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return 0;
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}
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uint32_t fm10k_mem_spi_EnableSectorProtection(uintptr_t mem) {
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SPI_CTRL currentSpiCtrl;
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SPI_CTRL spiCtrl = {0};
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uint32_t header;
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int32_t freq;
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fm10k_mem_spi_Enable(mem);
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, ¤tSpiCtrl.value);
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if (FM10K_SPI_FREQ_KHZ > 0) {
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freq = ((100000 / (int) FM10K_SPI_FREQ_KHZ) / 2) - 1;
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if (freq < 0) {
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freq = 0;
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}
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spiCtrl.fields.Freq = freq;
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}
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spiCtrl.fields.Enable = 1;
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header = (0x3D << 24) | (0x2A << 16) | (0x7F) | (0xA9);
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WriteRegister32(mem, FM10K_REGISTER_SPI_HEADER, header);
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/* first loop only: set send header flag. Following loops: shift only data. */
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spiCtrl.fields.Command |= 0x1;
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/* send command to the flash */
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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/* release CS */
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spiCtrl.fields.Command = 0x8;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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fm10k_mem_spi_Disable(mem);
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return 0;
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}
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uint32_t fm10k_mem_spi_DisableSectorProtection(uintptr_t mem) {
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SPI_CTRL currentSpiCtrl;
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SPI_CTRL spiCtrl = {0};
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uint32_t header;
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int32_t freq;
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fm10k_mem_spi_Enable(mem);
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, ¤tSpiCtrl.value);
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if (FM10K_SPI_FREQ_KHZ > 0) {
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freq = ((100000 / (int) FM10K_SPI_FREQ_KHZ) / 2) - 1;
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if (freq < 0) {
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freq = 0;
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}
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spiCtrl.fields.Freq = freq;
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}
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spiCtrl.fields.Enable = 1;
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header = (0x3D << 24) | (0x2A << 16) | (0x7F) | (0x9A);
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WriteRegister32(mem, FM10K_REGISTER_SPI_HEADER, header);
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/* first loop only: set send header flag. Following loops: shift only data. */
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spiCtrl.fields.Command |= 0x1;
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/* send command to the flash */
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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/* release CS */
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spiCtrl.fields.Command = 0x8;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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fm10k_mem_spi_Disable(mem);
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return 0;
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}
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uint32_t fm10k_mem_spi_WriteFlash(uintptr_t mem, uint32_t address, const uint8_t *data, uint32_t len) {
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SPI_CTRL currentSpiCtrl;
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SPI_CTRL spiCtrl = {0};
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uint32_t txData;
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uint32_t header;
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int32_t freq;
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uint32_t cnt;
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uint32_t numWrite;
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fm10k_mem_spi_Enable(mem);
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ReadRegister32(mem, FM10K_REGISTER_SPI_CTRL, ¤tSpiCtrl.value);
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if (FM10K_SPI_FREQ_KHZ > 0) {
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freq = ((100000 / (int) FM10K_SPI_FREQ_KHZ) / 2) - 1;
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if (freq < 0) {
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freq = 0;
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}
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spiCtrl.fields.Freq = freq;
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}
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spiCtrl.fields.Enable = 1;
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/* header: command (1 byte: READ_MODIFY_WRITE) + address (3 bytes) */
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header = (FM10K_SPI_HEADER_COMMAND_READ_MODIFY_WRITE_512 << 24) | (address & 0xffffff);
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WriteRegister32(mem, FM10K_REGISTER_SPI_HEADER, header);
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/* first loop only: set send header flag. Following loops: shift only data. */
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spiCtrl.fields.Command |= 0x1;
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cnt = 0;
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while (cnt < len) {
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/* determine the number of data bytes to read [1..4] */
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numWrite = (len - cnt) > 3 ? 4 : (len - cnt);
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/* set 'shift data' flag and number of data bytes */
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spiCtrl.fields.Command |= 0x4;
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spiCtrl.fields.DataSize = numWrite & 3;
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txData = 0;
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while (numWrite--) {
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txData = (txData << 8) | data[cnt++];
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}
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/* set data to be written */
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WriteRegister32(mem, FM10K_REGISTER_SPI_TX_DATA, txData);
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/* send command to the flash */
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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spiCtrl.fields.Command = 0;
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spiCtrl.fields.DataSize = 0;
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}
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/* release CS */
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spiCtrl.fields.Command = 0x8;
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if (fm10k_mem_spi_SetCtrlReg(mem, spiCtrl)) {
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return 1;
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}
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fm10k_mem_spi_Disable(mem);
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return 0;
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}
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const KNOWN_FLASH_DEVICE *getKnownFlashFromManufacturerData(SPI_COMMAND_READ_MANUFACTURER_RESULT data) {
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uint32_t deviceCount = (sizeof(KNOWN_FLASH_DEVICE_LIST) / sizeof(KNOWN_FLASH_DEVICE)) - 1;
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for (uint32_t i = 0; i < deviceCount; ++i) {
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if (KNOWN_FLASH_DEVICE_LIST[i].data.value == data.value) {
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return &KNOWN_FLASH_DEVICE_LIST[i];
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}
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}
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return NULL;
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}
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uint8_t fm10k_mem_spi_LockTake(uintptr_t mem){
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uint32_t maxTries = 64;
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API_SPI_LOCK_STATE spiLock;
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do{
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ReadRegister32(mem, FM10K_API_SPI_LOCK_STATE, &spiLock.value);
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if(!spiLock.fields.LockTaken){
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spiLock.fields.LockTaken = 1;
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spiLock.fields.LockOwner = 0; //Switch API
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WriteRegister32(mem, FM10K_API_SPI_LOCK_STATE, spiLock.value);
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nanosleep(&(struct timespec){0, 50000}, NULL); //Delay to observe if lock was actually taken by us
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ReadRegister32(mem, FM10K_API_SPI_LOCK_STATE, &spiLock.value);
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if(spiLock.fields.LockTaken && spiLock.fields.LockOwner == 0){
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printf("Taken SPI Lock\n");
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return 0;
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}
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}else if(spiLock.fields.LockOwner == 0){ //Are we taking a lock again, with same owner?
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printf("WARNING: SPI Lock was already taken by us, maybe other process was using it?\n");
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return 0;
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}
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nanosleep(&(struct timespec){0, 1000}, NULL);
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} while (--maxTries);
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return 1;
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}
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void fm10k_mem_spi_LockRelease(uintptr_t mem){
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API_SPI_LOCK_STATE spiLock;
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ReadRegister32(mem, FM10K_API_SPI_LOCK_STATE, &spiLock.value);
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if(!spiLock.fields.LockTaken) {
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printf("WARNING: SPI Lock was already released\n");
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return;
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}
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if(spiLock.fields.LockOwner != 0){
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printf("WARNING: SPI Lock Owner unexpected: %u\n", spiLock.fields.LockOwner);
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return;
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}
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spiLock.fields.LockTaken = 0;
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WriteRegister32(mem, FM10K_API_SPI_LOCK_STATE, spiLock.value);
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printf("Released SPI Lock\n");
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}
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uint32_t bsm_interruptMask[2] = {0, 0};
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void fm10k_mem_bsm_DisableInterrupts(uintptr_t mem){
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//Save old registers
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ReadRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(0), bsm_interruptMask);
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ReadRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(1), bsm_interruptMask + 1);
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WriteRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(0), 0xFFFFFFFF);
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WriteRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(1), 0xFFFFFFFF);
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}
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void fm10k_mem_bsm_RestoreInterrupts(uintptr_t mem){
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WriteRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(0), bsm_interruptMask[0]);
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WriteRegister32(mem, FM10K_REGISTER_INTERRUPT_MASK_BSM(1), bsm_interruptMask[1]);
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}
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uint8_t fm10k_mem_TakePlatformLock(uintptr_t mem){
|
|
if(fm10k_mem_spi_LockTake(mem)){
|
|
return 1;
|
|
}
|
|
fm10k_mem_bsm_DisableInterrupts(mem);
|
|
return 0;
|
|
}
|
|
|
|
void fm10k_mem_ReleasePlatformLock(uintptr_t mem){
|
|
fm10k_mem_spi_LockRelease(mem);
|
|
fm10k_mem_bsm_RestoreInterrupts(mem);
|
|
}
|
|
|
|
int fm10k_pci_unmapDevice(FM10K_PCI_MAPPED_DEVICE* map){
|
|
if(map->map != NULL && map->map != MAP_FAILED){
|
|
if(munmap(map->map, FM10K_BAR4_SIZE) != 0){
|
|
return 1;
|
|
}
|
|
map->map = NULL;
|
|
}
|
|
|
|
if (map->fd > 0) {
|
|
if(close(map->fd) != 0){
|
|
return 1;
|
|
}
|
|
map->fd = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fm10k_pci_mapDevice(const FM10K_PCI_DEVICE* device, FM10K_PCI_MAPPED_DEVICE* map){
|
|
int fdBAR4;
|
|
fdBAR4 = open(device->bar4Path, O_RDWR);
|
|
if (fdBAR4 <= 0) {
|
|
printf("Unable to open BAR4 resource %s to read NVM\n", device->bar4Path);
|
|
return 1;
|
|
}
|
|
|
|
void *memmapAddr;
|
|
memmapAddr = mmap(NULL, FM10K_BAR4_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fdBAR4, 0);
|
|
if (memmapAddr == MAP_FAILED) {
|
|
printf("Unable to map BAR4 resource %s to read NVM\n", device->bar4Path);
|
|
close(fdBAR4);
|
|
return 1;
|
|
}
|
|
|
|
map->device = device;
|
|
map->fd = fdBAR4;
|
|
map->map = memmapAddr;
|
|
|
|
if(fm10k_mem_TakePlatformLock((uintptr_t) map->map)){
|
|
//Error taking lock
|
|
fm10k_pci_unmapDevice(map);
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fm10k_pci_findDevice(const FM10K_PCI_DEVICES* devices, FM10K_PCI_MAPPED_DEVICE* map) {
|
|
if(devices->count == 0){
|
|
return 1;
|
|
}
|
|
|
|
for(uint32_t i = 0; i < devices->count; ++i){
|
|
if(fm10k_pci_mapDevice(&devices->devices[i], map) == 0){
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
FM10K_PCI_DEVICES fm10k_pci_findDevices() {
|
|
DIR *folder;
|
|
char fileName[PATH_MAX];
|
|
FM10K_PCI_DEVICES devices;
|
|
devices.count = 0;
|
|
|
|
folder = opendir("/sys/bus/pci/devices");
|
|
if (folder == NULL) {
|
|
return devices;
|
|
}
|
|
|
|
struct dirent *entry;
|
|
while ((entry = readdir(folder))) {
|
|
if (entry->d_type == DT_DIR || entry->d_type == DT_LNK) {
|
|
sprintf(fileName, "/sys/bus/pci/devices/%s/vendor", entry->d_name);
|
|
|
|
FILE *vendorBytesPointer = fopen(fileName, "rb");
|
|
if (vendorBytesPointer != NULL) {
|
|
char *vendorBytesBuffer = NULL;
|
|
size_t vendorBytesLen;
|
|
size_t vendorBytesRead = getdelim(&vendorBytesBuffer, &vendorBytesLen, '\0', vendorBytesPointer);
|
|
if (vendorBytesRead != -1) {
|
|
unsigned int vendor = (unsigned int) strtoul(vendorBytesBuffer, NULL, 0);
|
|
|
|
if (vendor == 0x8086) { //Intel Corporation
|
|
|
|
sprintf(fileName, "/sys/bus/pci/devices/%s/device", entry->d_name);
|
|
FILE *classBytesPointer = fopen(fileName, "rb");
|
|
if (classBytesPointer != NULL) {
|
|
char *classBytesBuffer = NULL;
|
|
size_t classBytesLen;
|
|
size_t classBytesRead = getdelim(&classBytesBuffer, &classBytesLen, '\0',
|
|
classBytesPointer);
|
|
if (classBytesRead != -1) {
|
|
unsigned int class = (unsigned int) strtoul(classBytesBuffer, NULL, 0);
|
|
|
|
if (class == 0x15a4 || class == 0x15d0 || class == 0x15d5) { //FM10000 devices
|
|
sprintf(fileName, "/sys/bus/pci/devices/%s/resource4", entry->d_name);
|
|
if (access(fileName, F_OK) == 0) {
|
|
devices.devices[devices.count].vendor = vendor;
|
|
devices.devices[devices.count].class = class;
|
|
|
|
sprintf(devices.devices[devices.count].bar4Path, "/sys/bus/pci/devices/%s/resource4", entry->d_name);
|
|
++devices.count;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (classBytesBuffer != NULL) {
|
|
free(classBytesBuffer);
|
|
}
|
|
fclose(classBytesPointer);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (vendorBytesBuffer != NULL) {
|
|
free(vendorBytesBuffer);
|
|
}
|
|
fclose(vendorBytesPointer);
|
|
}
|
|
|
|
if (devices.count >= FM10K_PCI_DEVICE_MAX) {
|
|
break;
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
closedir(folder);
|
|
|
|
return devices;
|
|
}
|