FM10K/fsm
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Provide register mapping

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This commit is contained in:
DataHoarder 2021-10-24 22:54:16 +02:00
parent e542e41319
commit 3148925051
5 changed files with 751 additions and 28 deletions
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2
CMakeLists.txt
View file

@ -5,5 +5,5 @@ set(CMAKE_CXX_STANDARD 14)
include_directories(${fsm_SOURCE_DIR}/src)
add_executable(fsmd src/fsmd.cpp src/device/PCIEDevice.cpp src/device/PCIEDevice.h src/fm10k/FM10K.cpp src/fm10k/FM10K.h src/fm10k/Functions.h src/fm10k/Functions.cpp)
add_executable(fsmd src/fsmd.cpp src/device/PCIEDevice.cpp src/fm10k/FM10K.cpp src/fm10k/Functions.cpp)
add_executable(fsm src/fsm.cpp)

54
src/fm10k/FM10K.cpp
View file

@ -1 +1,55 @@
#include "FM10K.h"
#include "registers/Register.h"
const FM10K::FM10K::HardwareInformation& FM10K::FM10K::getHardwareInformation() const {
return m_hwInfo;
}
std::string FM10K::FM10K::getHardwareInformationString() const {
auto& info = getHardwareInformation();
std::string s;
s.reserve(2);
if(info.family != HardwareInformation::Family::FM10000){
return "unknown";
}
switch (info.model) {
default:
s += "FM10000-unknown";
break;
case HardwareInformation::Model::FM10840:
s += "FM10840";
break;
case HardwareInformation::Model::FM10420:
s += "FM10420";
break;
case HardwareInformation::Model::FM10824:
s += "FM10824";
break;
case HardwareInformation::Model::FM10064:
s += "FM10064";
break;
case HardwareInformation::Model::FM10036:
s += "FM10036";
break;
}
switch (info.chipVersion) {
default:
s += "_unknown";
break;
case HardwareInformation::ChipVersion::A0:
s += "_A0";
break;
case HardwareInformation::ChipVersion::B0:
s += "_B0";
break;
}
return s;
}

45
src/fm10k/FM10K.h
View file

@ -22,7 +22,23 @@ namespace FM10K{
public:
explicit FM10K(std::unique_ptr<Device> device) : m_device(std::move(device)) {
if(valid()){
auto vpd = FM10K_MAP_REGISTER((*this), registers::MGMT::VITAL_PRODUCT_DATA);
auto chipVersion = FM10K_MAP_REGISTER((*this), registers::MGMT::CHIP_VERSION);
auto fuseData = FM10K_MAP_REGISTER((*this), registers::MGMT::FUSE_DATA_0);
m_hwInfo = {
static_cast<HardwareInformation::Family>(vpd->fields.PartNumber),
static_cast<HardwareInformation::Model>(fuseData->fields.SKU),
static_cast<HardwareInformation::ChipVersion>(chipVersion->fields.Version),
};
} else {
m_hwInfo = {};
}
}
bool valid() const{
return m_device->valid();
}
template<typename T> volatile T* mapType(uint32_t address) const {
@ -45,10 +61,39 @@ namespace FM10K{
return std::move(t);
}
struct HardwareInformation{
enum class Family{
FM10000 = 0xAE21
};
enum class Model{
// FMxppbb, x = series number, pp = Number of PCIe data ports, bb = Ethernet port bandwidth
//
// +- Max Ethernet Port Usage -+- PCIe Data -+- Estimated -+-----+--------------------------+
// | 100G | 40G | 10G | SGMII | Ports | WC Power | ROM | Use Cases |
// +-------+-----+-----+-------+-------------+-------------+-----+--------------------------+
FM10840 = 0, // | 4 | 9 | 36 | 36 | 8x4, 4x8 | 50 W | Yes | High perf compute fabric |
FM10420 = 1, // | 2 | 2 | 8 | 8 | 4x4, 2x8 | 38 W | Yes | Low cost compute fabric |
FM10824 = 2, // | 0 | 6 | 24 | 36 | 8x4, 4x8 | 43 W | No | 10G/40G/100GbE NIC |
FM10064 = 3, // | 6 | 9 | 36 | 36 | 0 | 47 W | No | Microserver switch |
FM10036 = 4 // | 0 | 0 | 0 | 0 | 0 | 39 W | No | Low cost 10GbE switch |
// +-------+-----+-----+-------+-------------+-------------+-----+--------------------------+
};
enum class ChipVersion{
A0 = 0,
B0 = 1
};
Family family;
Model model;
ChipVersion chipVersion;
};
const HardwareInformation& getHardwareInformation() const;
std::string getHardwareInformationString() const;
private:
std::unique_ptr<Device> m_device;
HardwareInformation m_hwInfo;
};
}

669
src/fm10k/registers/MGMT.h
View file

@ -2,46 +2,671 @@
#include "Register.h"
namespace FM10K{
namespace registers{
namespace MGMT{
enum class DEVICE_CFG_FeatureCode: uint8_t {
namespace FM10K {
namespace registers {
namespace MGMT {
enum class DEVICE_CFG_FeatureCode : uint8_t {
FULL = 0b00,
HALF = 0b01,
BASIC = 0b10,
RESERVED = 0b11,
};
enum class PLL_PCIE_CTRL_OutMuxSel : uint8_t {
PLL_PCIE_CTRL_OutMuxSel_PCIE_REFCLK = 0b000,
PLL_PCIE_CTRL_OutMuxSel_PLL_PCIE_CLK = 0b001,
PLL_PCIE_CTRL_OutMuxSel_BURN_IN_CLK = 0b010
//Rest of values are reserved
};
typedef PACKED(struct {
uint8_t PCIeMode: 4; //Bitfield array [0..3]
uint8_t Eth100GDisabled: 1;
DEVICE_CFG_FeatureCode FeatureCode: 2;
uint16_t PCIeEnable: 9; //Bitfield array [0..8]
uint8_t SystimeClockSource: 1;
uint16_t : 15;
}, uint32_t) DEVICE_CFG;
uint8_t FatalCode: 8;
uint32_t Reserved: 24;
}, uint32_t) FATAL_CODE;
typedef PACKED(struct {
uint8_t FatalCode: 8;
uint32_t Reserved: 24;
}, uint32_t) LAST_FATAL_CODE;
typedef PACKED(struct {
uint8_t ResetCount: 8;
uint32_t Reserved: 24;
}, uint32_t) FATAL_COUNT;
typedef PACKED(struct {
uint8_t ColdReset: 1;
uint8_t EPLReset: 1;
uint8_t SwitchReset: 1;
uint8_t SwitchReady: 1;
uint16_t PCIeReset: 9; //Bitfield array [0..8]
uint16_t PCIeActive: 9; //Bitfield array [0..8]
uint16_t Reserved: 10;
}, uint32_t) SOFT_RESET;
const uint32_t SOFT_RESET__Address = 0x3;
typedef PACKED(struct {
uint8_t PCIeMode: 4; //Bitfield array [0..3]
uint8_t Eth100GDisabled: 1;
DEVICE_CFG_FeatureCode FeatureCode: 2;
uint16_t PCIeEnable: 9; //Bitfield array [0..8]
uint8_t SystimeClockSource: 1;
uint16_t Reserved: 15;
}, uint32_t) DEVICE_CFG;
const uint32_t DEVICE_CFG__Address = 0x4;
typedef PACKED(struct {
uint8_t MasterResetAssertCount: 8;
uint8_t MasterResetDelayCount: 8;
uint16_t Reserved: 16;
}, uint32_t) RESET_CFG;
typedef PACKED(struct {
uint8_t FatalResetEnable: 1;
uint32_t Reserved: 31;
}, uint32_t) WATCHDOG_CFG;
typedef PACKED(struct {
uint16_t PartNumber : 16;
uint16_t : 16;
}, uint32_t) VITAL_PRODUCT_DATA;
uint16_t PartNumber: 16;
uint16_t Reserved: 16;
}, uint32_t) VITAL_PRODUCT_DATA;
const uint32_t VITAL_PRODUCT_DATA__Address = 0x304;
typedef PACKEDM(struct {
uint16_t PCIE_BSM: 9; //Bitfield array [0..8]
uint16_t PCIE: 9; //Bitfield array [0..8]
uint16_t EPL: 9; //Bitfield array [0..8]
uint16_t TUNNEL: 2; //Bitfield array [0..1]
uint8_t CORE: 1;
uint8_t SOFTWARE: 1;
uint8_t GPIO: 1;
uint8_t I2C: 1;
uint8_t MDIO: 1;
uint8_t CRM: 1;
uint8_t FH_TAIL: 1;
uint8_t FH_HEAD: 1;
uint8_t SBUS_EPL: 1;
uint8_t SBUS_PCIE: 1;
uint8_t PINS: 1;
uint8_t FIBM: 1;
uint8_t BSM: 1;
uint8_t XCLK: 1;
uint32_t Reserved: 21;
}, uint32_t, 2) GLOBAL_INTERRUPT_DETECT;
typedef PACKEDM(struct {
uint16_t PCIE_BSM: 9; //Bitfield array [0..8]
uint16_t PCIE: 9; //Bitfield array [0..8]
uint16_t EPL: 9; //Bitfield array [0..8]
uint16_t TUNNEL: 2; //Bitfield array [0..1]
uint8_t CORE: 1;
uint8_t SOFTWARE: 1;
uint8_t GPIO: 1;
uint8_t I2C: 1;
uint8_t MDIO: 1;
uint8_t CRM: 1;
uint8_t FH_TAIL: 1;
uint8_t FH_HEAD: 1;
uint8_t SBUS_EPL: 1;
uint8_t SBUS_PCIE: 1;
uint8_t PINS: 1;
uint8_t FIBM: 1;
uint8_t BSM: 1;
uint8_t XCLK: 1;
uint32_t Reserved: 21;
}, uint32_t, 2) INTERRUPT_MASK_INT;
typedef PACKEDM(struct {
uint16_t PCIE_BSM: 9; //Bitfield array [0..8]
uint16_t PCIE: 9; //Bitfield array [0..8]
uint16_t EPL: 9; //Bitfield array [0..8]
uint16_t TUNNEL: 2; //Bitfield array [0..1]
uint8_t CORE: 1;
uint8_t SOFTWARE: 1;
uint8_t GPIO: 1;
uint8_t I2C: 1;
uint8_t MDIO: 1;
uint8_t CRM: 1;
uint8_t FH_TAIL: 1;
uint8_t FH_HEAD: 1;
uint8_t SBUS_EPL: 1;
uint8_t SBUS_PCIE: 1;
uint8_t PINS: 1;
uint8_t FIBM: 1;
uint8_t BSM: 1;
uint8_t XCLK: 1;
uint32_t Reserved: 21;
}, uint32_t, 2) INTERRUPT_MASK_PCIE; // [0..8]
typedef PACKEDM(struct {
uint16_t PCIE_BSM: 9; //Bitfield array [0..8]
uint16_t PCIE: 9; //Bitfield array [0..8]
uint16_t EPL: 9; //Bitfield array [0..8]
uint16_t TUNNEL: 2; //Bitfield array [0..1]
uint8_t CORE: 1;
uint8_t SOFTWARE: 1;
uint8_t GPIO: 1;
uint8_t I2C: 1;
uint8_t MDIO: 1;
uint8_t CRM: 1;
uint8_t FH_TAIL: 1;
uint8_t FH_HEAD: 1;
uint8_t SBUS_EPL: 1;
uint8_t SBUS_PCIE: 1;
uint8_t PINS: 1;
uint8_t FIBM: 1;
uint8_t BSM: 1;
uint8_t XCLK: 1;
uint32_t Reserved: 21;
}, uint32_t, 2) INTERRUPT_MASK_FIBM;
typedef PACKEDM(struct {
uint16_t PCIE_BSM: 9; //Bitfield array [0..8]
uint16_t PCIE: 9; //Bitfield array [0..8]
uint16_t EPL: 9; //Bitfield array [0..8]
uint16_t TUNNEL: 2; //Bitfield array [0..1]
uint8_t CORE: 1;
uint8_t SOFTWARE: 1;
uint8_t GPIO: 1;
uint8_t I2C: 1;
uint8_t MDIO: 1;
uint8_t CRM: 1;
uint8_t FH_TAIL: 1;
uint8_t FH_HEAD: 1;
uint8_t SBUS_EPL: 1;
uint8_t SBUS_PCIE: 1;
uint8_t PINS: 1;
uint8_t FIBM: 1;
uint8_t BSM: 1;
uint8_t XCLK: 1;
uint32_t Reserved: 21;
}, uint32_t, 2) INTERRUPT_MASK_BSM;
typedef PACKED(struct {
uint16_t ChipVersion : 7;
uint32_t : 25;
}, uint32_t) CHIP_VERSION;
uint8_t MODIFY: 1;
uint8_t FH_HEAD: 1;
uint8_t FH_TAIL: 1;
uint8_t SCHEDULER: 1;
uint32_t Reserved: 25;
uint8_t SRAM_ERR: 1;
uint8_t INGRESS_ERR: 1;
uint8_t EGRESS_ERR: 1;
}, uint32_t) CORE_INTERRUPT_DETECT;
typedef PACKED(struct {
uint8_t MODIFY: 1;
uint8_t FH_HEAD: 1;
uint8_t FH_TAIL: 1;
uint8_t SCHEDULER: 1;
uint32_t Reserved: 25;
uint8_t SRAM_ERR: 1;
uint8_t INGRESS_ERR: 1;
uint8_t EGRESS_ERR: 1;
}, uint32_t) CORE_INTERRUPT_MASK;
typedef PACKEDM(struct {
uint32_t Error_0: 32; //Bitfield array [0..31]
uint32_t Error_1: 32; //Bitfield array [32..47]
uint16_t Reserved: 16;
}, uint32_t, 2) SRAM_ERR_IP;
typedef PACKEDM(struct {
uint32_t Mask_0: 32; //Bitfield array [0..31]
uint32_t Mask_1: 32; //Bitfield array [32..47]
uint16_t Reserved: 16;
}, uint32_t, 2) SRAM_ERR_IM;
typedef PACKED(struct {
uint16_t PCIE_RESET_N: 9; //Bitfield array [0..8]
uint32_t Reserved: 23;
}, uint32_t) PINS_STAT;
typedef PACKED(struct {
uint16_t DataDetectHigh: 9; //Bitfield array [0..8]
uint8_t Reserved: 7;
uint16_t DataDetectLow: 9; //Bitfield array [0..8]
uint8_t Reserved2: 7;
}, uint32_t) PINS_IP;
typedef PACKED(struct {
uint16_t MaskDetectHigh: 9; //Bitfield array [0..8]
uint8_t Reserved: 7;
uint16_t MaskDetectLow: 9; //Bitfield array [0..8]
uint8_t Reserved2: 7;
}, uint32_t) PINS_IM;
typedef PACKED(struct {
uint16_t Data: 16;
uint16_t Mask: 16;
}, uint32_t) SW_TEST_AND_SET;
typedef PACKED(struct {
uint8_t SelC: 4;
uint8_t DivC: 2; //TODO: enum
uint32_t Reserved: 26;
}, uint32_t) LSM_CLKOBS_CTRL;
typedef PACKED(struct {
uint16_t Version: 7;
uint32_t Reserved: 25;
}, uint32_t) CHIP_VERSION;
const uint32_t CHIP_VERSION__Address = 0x452;
typedef PACKED(struct {
uint16_t : 11;
uint8_t SKU : 5;
uint8_t VDDS_VRM : 8;
uint8_t VDDF_VRM : 8;
}, uint32_t) FUSE_DATA_0;
uint8_t Command: 4;
uint8_t CommandDone: 1;
uint8_t EepromLoadDone: 1;
uint8_t EepromError: 1;
uint8_t EepromEnable: 1;
uint32_t EepromAddr: 24;
}, uint32_t) BSM_CTRL;
typedef PACKED(struct {
uint8_t ErrWrite: 2; //TODO: enum
uint8_t CErr: 1;
uint8_t UErr: 1;
uint8_t BistDonePass: 1;
uint8_t BistDoneFail: 1;
uint32_t Reserved: 26;
}, uint32_t) BSM_SRAM_CTRL;
typedef PACKED(struct {
uint8_t SramErr: 2; //Bitfield array [0..1]
uint32_t Reserved: 30;
}, uint32_t) BSM_IP;
typedef PACKED(struct {
uint8_t SramErr: 2; //Bitfield array [0..1]
uint32_t Reserved: 30;
}, uint32_t) BSM_IM;
typedef PACKED(struct {
uint8_t ethClkTerm: 1;
uint8_t pcieClkTerm: 1;
uint8_t ieee1588ClkTerm: 1;
uint32_t Reserved: 29;
}, uint32_t) PIN_STRAP_STAT;
typedef PACKED(struct {
uint16_t : 11;
uint8_t SKU: 5;
uint8_t VDDS_VRM: 8;
uint8_t VDDF_VRM: 8;
}, uint32_t) FUSE_DATA_0;
const uint32_t FUSE_DATA_0__Address = 0xC0E;
typedef PACKED(struct {
uint32_t : 32;
}, uint32_t) FUSE_DATA_1;
const uint32_t FUSE_DATA_1__Address = 0xC0F;
typedef PACKEDM(struct {
uint16_t BistRun_PCIE: 9; //Bitfield array [0..8]
uint8_t BistRun_EPL: 1;
uint8_t BistRun_FABRIC: 1;
uint8_t BistRun_TUNNEL: 1;
uint8_t BistRun_BSM: 1;
uint8_t BistRun_CRM: 1;
uint8_t BistRun_FIBM: 1;
uint8_t BistRun_SBM: 1;
uint16_t Reserved: 16;
uint16_t BistMode_PCIE: 9; //Bitfield array [0..8]
uint8_t BistMode_EPL: 1;
uint8_t BistMode_FABRIC: 1;
uint8_t BistMode_TUNNEL: 1;
uint8_t BistMode_BSM: 1;
uint8_t BistMode_CRM: 1;
uint8_t BistMode_FIBM: 1;
uint8_t BistMode_SBM: 1;
uint16_t Reserved2: 16;
}, uint32_t, 2) BIST_CTRL;
typedef PACKED(struct {
uint8_t Reset: 1;
uint8_t Mode: 1;
uint8_t Run: 1;
uint8_t AutoLoadEnable: 1;
uint32_t Reserved: 28;
}, uint32_t) REI_CTRL;
typedef PACKED(struct {
uint8_t ReiDonePass: 1;
uint8_t ReiDoneFail: 1;
uint32_t Reserved: 30;
}, uint32_t) REI_STAT;
typedef PACKED(struct {
uint16_t Dir: 16; //Bitfield array [0..15]
uint16_t OpenDrain: 16; //Bitfield array [0..15]
}, uint32_t) GPIO_CFG;
typedef PACKED(struct {
//NOTE: Writing causes the value to be latched into a 16-bit latch, while reading returns the actual pin state.
volatile uint16_t data: 16; //Bitfield array [0..15]
uint16_t Reserved: 16;
}, uint32_t) GPIO_DATA;
typedef PACKED(struct {
uint16_t detectHigh: 16; //Bitfield array [0..15]
uint16_t detectLow: 16; //Bitfield array [0..15]
}, uint32_t) GPIO_IP;
typedef PACKED(struct {
uint16_t detectHighMask: 16; //Bitfield array [0..15]
uint16_t detectLowMask: 16; //Bitfield array [0..15]
}, uint32_t) GPIO_IM;
typedef PACKED(struct {
uint8_t Enable: 1;
uint8_t Addr: 7;
uint16_t Divider: 12; //TODO: enum
uint8_t InterruptMask: 1;
uint8_t DebounceFilterCountLimit: 7;
uint8_t Reserved: 4;
}, uint32_t) I2C_CFG;
typedef PACKED(struct {
uint8_t Addr: 7;
uint8_t Command: 2; //TODO: enum
uint8_t LengthW: 4;
uint8_t LengthR: 4;
uint8_t LengthSent: 4;
uint8_t CommandCompleted: 4;
uint8_t InterruptPending: 1;
uint8_t Reserved: 5;
}, uint32_t) I2C_CTRL;
typedef PACKED(struct {
uint16_t Divider: 12; //TODO: enum
uint8_t Preamble: 1;
uint8_t InterruptMask: 1;
uint32_t Reserved: 17;
}, uint32_t) MDIO_CFG;
typedef PACKED(struct {
uint16_t Data: 16;
uint16_t Reserved: 16;
}, uint32_t) MDIO_DATA;
typedef PACKED(struct {
uint16_t Register: 16;
uint8_t Device: 5;
uint8_t PhyAddress: 5;
uint8_t Command: 2; //TODO: enum
uint8_t DeviceType: 1;
uint8_t Status: 2; //TODO: enum
uint8_t InterruptPending: 1;
}, uint32_t) MDIO_CTRL;
typedef PACKED(struct {
uint16_t Freq: 10; //TODO: enum
uint8_t Enable: 1;
uint8_t Command_SendHeader: 1;
uint8_t Command_SendTurnAround: 1;
uint8_t Command_ShiftData: 1;
uint8_t Command_ReleaseChipSelect: 1;
uint8_t HeaderSize: 2;
uint8_t DataSize: 2;
uint8_t DataShiftMethod: 2; //TODO: enum
uint8_t Busy: 1;
uint8_t Selected: 1;
uint8_t DirIO2: 1;
uint8_t DirIO3: 1;
uint8_t PinIO2: 1;
uint8_t PinIO3: 1;
uint8_t Reserved: 5;
}, uint32_t) SPI_CTRL;
typedef PACKED(struct {
uint32_t LEDFreq: 24; //TODO: enum
uint8_t LEDEnable: 1;
uint8_t Reserved: 7;
}, uint32_t) LED_CFG;
typedef PACKED(struct {
uint32_t ScanData: 25;
uint8_t ShiftIn: 1;
uint8_t ShiftOut: 1;
uint8_t UpdateNodes: 1;
uint8_t Inject: 1;
uint8_t Drain: 1;
uint8_t Passthru: 1;
uint8_t Single: 1;
}, uint32_t) SCAN_DATA_IN;
const uint32_t SCAN_DATA_IN__Address = 0xC2D;
typedef PACKED(struct {
uint8_t Run: 1;
uint8_t FirstCommandIndex: 6;
uint8_t LastCommandIndex: 6;
uint8_t ContinuousRun: 1;
uint8_t TickPrescale: 5;
uint8_t TimeoutPrescale: 5;
uint8_t Reserved: 8;
}, uint32_t) CRM_CTRL;
typedef PACKED(struct {
uint8_t Running: 1;
uint8_t CommandIndex: 6;
uint32_t Reserved: 25;
}, uint32_t) CRM_STATUS;
typedef PACKED(struct {
uint32_t Tick: 32;
}, uint32_t) CRM_TIME;
typedef PACKEDM(struct {
uint16_t ErrWrite: 14; //2-bit Bitfield array [0..6]
uint16_t CErr: 14; //2-bit Bitfield array [0..6]
uint16_t UErr: 14; //2-bit Bitfield array [0..6]
uint16_t BistDonePass: 14; //2-bit Bitfield array [0..6]
uint16_t BistDoneFail: 14; //2-bit Bitfield array [0..6]
uint32_t Reserved: 22;
}, uint32_t, 2) CRM_SRAM_CTRL;
typedef PACKEDM(struct {
uint32_t InterruptPending_0: 32; //Bitfield array
uint32_t InterruptPending_1: 32; //Bitfield array
uint8_t SramErr: 2; //Bitfield array [0..1]
uint32_t Reserved1: 32;
uint32_t Reserved2: 29;
}, uint32_t, 4) CRM_IP;
typedef PACKEDM(struct {
uint32_t InterruptMask_0: 32; //Bitfield array
uint32_t InterruptMask_1: 32; //Bitfield array
uint8_t SramErr: 2; //Bitfield array [0..1]
uint32_t Reserved1: 32;
uint32_t Reserved2: 29;
}, uint32_t, 4) CRM_IM;
typedef PACKEDM(struct {
uint8_t Command: 3; //TODO: enum
uint16_t DataIndex: 10;
uint32_t Count: 19;
uint32_t Reserved: 29;
}, uint32_t, 2) CRM_COMMAND;
typedef PACKEDM(struct {
uint32_t BaseAddress: 24;
uint8_t Size: 2; //TODO: enum
uint8_t BlockSize1Shift: 4;
uint8_t Stride1Shift: 4;
uint8_t BlockSize2Shift: 4;
uint8_t Stride2Shift: 4;
uint32_t Reserved: 21;
}, uint32_t, 2) CRM_REGISTER;
typedef PACKEDM(struct {
uint32_t Interval: 32;
uint32_t LastTick: 32;
}, uint32_t, 2) CRM_PERIOD;
typedef PACKED(struct {
uint8_t Nreset: 1;
uint8_t Enable: 1;
uint8_t Halt: 1;
uint8_t RefDiv: 6;
uint8_t FbDiv4: 1;
uint8_t FbDiv255: 8;
uint8_t OutDiv: 6;
PLL_PCIE_CTRL_OutMuxSel OutMuxSel: 3; //TODO: enum
uint8_t Reserved: 5;
}, uint32_t) PLL_PCIE_CTRL;
typedef PACKED(struct {
uint8_t PllLocked: 1;
uint8_t PllFreqChange: 1;
uint8_t MiscCtrl_FastCalibrationMode: 1;
uint8_t MiscCtrl_SparePins: 3;
uint8_t MiscCtrl_AsyncLoadSignalPLLDiv: 1;
uint8_t MiscCtrl_Reserved: 1;
uint8_t MiscCtrl_InitialThermalBits: 2;
uint32_t Reserved: 22;
}, uint32_t) PLL_PCIE_STAT;
typedef PACKED(struct {
uint8_t SBUS_ControllerReset: 1;
uint8_t RomEnable: 1;
uint8_t RomBusy: 1;
uint8_t BistDonePass: 1;
uint8_t BistDoneFail: 1;
uint32_t Reserved: 27;
}, uint32_t) SBUS_PCIE_CFG;
typedef PACKED(struct {
uint8_t Register: 8;
uint8_t Address: 8;
uint8_t Op: 8;
uint8_t Execute: 1;
uint8_t Busy: 1;
uint8_t ResultCode: 3;
uint8_t Reserved: 3;
}, uint32_t) SBUS_PCIE_COMMAND;
typedef PACKED(struct {
uint8_t Interrupt: 1;
uint16_t GeneralPurposeIn: 16;
uint16_t Reserved: 15;
}, uint32_t) SBUS_PCIE_SPICO_IN;
typedef PACKED(struct {
uint16_t GeneralPurposeOut: 16;
uint16_t Reserved: 16;
}, uint32_t) SBUS_PCIE_SPICO_OUT;
typedef PACKED(struct {
uint16_t DataDetectHigh: 16;
uint16_t DataDetectLow: 16;
}, uint32_t) SBUS_PCIE_IP;
typedef PACKED(struct {
uint16_t MaskDataDetectHigh: 16;
uint16_t MaskDataDetectLow: 16;
}, uint32_t) SBUS_PCIE_IM;
typedef PACKEDM(struct {
uint8_t Reserved1: 4;
uint8_t STEP: 4;
uint8_t CaptureHigh: 4; //Bitfield array [0..3]
uint8_t CaptureLow: 4; //Bitfield array [0..3]
uint8_t Reserved2: 8;
uint32_t Adjust_1: 32;
uint8_t Adjust_2: 6;
uint8_t Reserved3: 1;
uint8_t Dir: 1;
}, uint32_t, 2) SYSTIME_CFG;
typedef PACKEDM(struct {
uint32_t CurrentTime_1: 32;
uint32_t CurrentTime_2: 32;
}, uint32_t, 2) SYSTIME;
typedef PACKEDM(struct {
uint32_t Time0_1: 32;
uint32_t Time0_2: 32;
}, uint32_t, 2) SYSTIME0;
typedef PACKEDM(struct {
uint32_t SampleTime_1: 32;
uint32_t SampleTime_2: 32;
}, volatile const uint32_t, 2) SYSTIME_CAPTURE;
typedef PACKED(struct {
uint8_t RefDiv: 6;
uint8_t FbDiv4: 1;
uint8_t FbDiv255: 8;
uint8_t OutDiv: 6;
uint8_t MiscCtrl: 8; //TODO: enum
uint8_t Reserved: 3;
}, uint32_t) PCIE_XPLL_CTRL;
typedef PACKEDM(struct {
uint8_t Nreset: 4; //Bitfield array [0..3]
uint8_t Enable: 4; //Bitfield array [0..3]
uint8_t Halt: 4; //Bitfield array [0..3]
uint8_t OutMuxSel: 8; // 2-bit Bitfield array [0..3]
uint16_t Mode: 12; // 3-bit Bitfield array [0..3]
uint8_t XclkTerm: 4; //Bitfield array [0..3]
uint8_t ClkObs: 4;
uint32_t Reserved: 24;
}, uint32_t, 2) PCIE_CLK_CTRL; //second part also named PCIE_CLK_CTRL2
typedef PACKED(struct {
uint16_t Denom: 16;
uint16_t Num: 16;
}, uint32_t) PCIE_CLKMON_RATIO_CFG;
typedef PACKED(struct {
uint16_t NegTol: 16;
uint16_t PosTol: 16;
}, uint32_t) PCIE_CLKMON_TOLERANCE_CFG;
typedef PACKED(struct {
uint16_t Sustain: 16;
uint16_t SilentLimit: 16;
}, uint32_t) PCIE_CLKMON_DEADLINES_CFG;
typedef PACKED(struct {
uint8_t PllLocked: 4; //Bitfield array [0..3]
uint8_t PllFreqChange: 4; //Bitfield array [0..3]
uint8_t RefclkSel: 4; //Bitfield array [0..3]
uint8_t XRefclkValid: 4; //Bitfield array [0..3]
uint16_t Reserved: 16;
}, uint32_t) PCIE_CLK_STAT;
typedef PACKED(struct {
uint8_t XRefClkValidChangeHigh: 4; //Bitfield array [0..3]
uint8_t XRefClkValidChangeLow: 4; //Bitfield array [0..3]
uint8_t XPllLockChangeHigh: 4; //Bitfield array [0..3]
uint8_t XPllLockChangeLow: 4; //Bitfield array [0..3]
uint16_t Reserved: 16;
}, uint32_t) PCIE_CLK_IP;
typedef PACKED(struct {
uint8_t XRefClkValidChangeHigh: 4; //Bitfield array [0..3]
uint8_t XRefClkValidChangeLow: 4; //Bitfield array [0..3]
uint8_t XPllLockChangeHigh: 4; //Bitfield array [0..3]
uint8_t XPllLockChangeLow: 4; //Bitfield array [0..3]
uint16_t Reserved: 16;
}, uint32_t) PCIE_CLK_IM;
typedef PACKED(struct {
uint16_t DelayCount: 16;
uint16_t Reserved: 16;
}, uint32_t) PCIE_WARM_RESET_DELAY;
}
}

9
src/fsmd.cpp
View file

@ -27,16 +27,15 @@ int main() {
FM10K::FM10K fm10k(std::move(dev));
std::cout << "Device Model_Stepping: " << fm10k.getHardwareInformationString() << std::endl;
auto fuseData_0 = FM10K_MAP_REGISTER(fm10k, FM10K::registers::MGMT::FUSE_DATA_0);
std::cout << "FUSE_DATA_0: " << tohex(fuseData_0->value) << std::endl;
std::cout << "FUSE_DATA_0.SKU: " << std::to_string(fuseData_0->fields.SKU) << std::endl;
std::cout << "FUSE_DATA_0.VDDF_VRM: " << std::to_string(fuseData_0->fields.VDDS_VRM) << std::endl;
std::cout << "FUSE_DATA_0.VDDF_VRM: " << std::to_string(fuseData_0->fields.VDDF_VRM) << std::endl;
std::cout << "FUSE_DATA_0.VDDF_VRM: " << FM10K::VR12_VID_to_Millivolts(fuseData_0->fields.VDDS_VRM) << std::endl;
std::cout << "FUSE_DATA_0.VDDF_VRM: " << FM10K::VR12_VID_to_Millivolts(fuseData_0->fields.VDDF_VRM) << std::endl;
auto deviceCfg = FM10K_MAP_REGISTER(fm10k, FM10K::registers::MGMT::DEVICE_CFG);
std::cout << "DEVICE_CFG: " << tohex(deviceCfg->value) << std::endl;
auto vpd = FM10K_MAP_REGISTER(fm10k, FM10K::registers::MGMT::VITAL_PRODUCT_DATA);
std::cout << "VITAL_PRODUCT_DATA.PartNumber: " << tohex(vpd->fields.PartNumber) << std::endl;
}
return 0;
}