Added IES initialization, config write
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parent
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commit
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3
.gitignore
vendored
3
.gitignore
vendored
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@ -1,3 +1,4 @@
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/cmake-build-debug
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/build
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.idea
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.idea
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/deps/IES/build
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2
.gitmodules
vendored
2
.gitmodules
vendored
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@ -1,3 +1,3 @@
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[submodule "deps/IES"]
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path = deps/IES
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url = https://git.gammaspectra.live/Sillycom/IES
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url = https://git.gammaspectra.live/FM10K/IES
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@ -3,8 +3,8 @@ project(fsm)
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set(CMAKE_CXX_STANDARD 14)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -D_FM_ARCH_64 -DFM_SUPPORT_FM10000 -D_GNU_SOURCE")
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_FM_ARCH_64 -DFM_SUPPORT_FM10000 -D_GNU_SOURCE")
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fno-exceptions -frtti -D_FM_ARCH_64 -DFM_SUPPORT_FM10000 -D_GNU_SOURCE")
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-exceptions -frtti -D_FM_ARCH_64 -DFM_SUPPORT_FM10000 -D_GNU_SOURCE")
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set(CMAKE_LD_FLAGS "${CMAKE_LD_FLAGS} -Wl,--no-as-needed")
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include_directories(src)
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@ -20,11 +20,6 @@ include_directories(deps/IES/build/include/platforms/libertyTrail)
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find_library(libFocalpointSDK NAMES FocalpointSDK PATHS ${PROJECT_SOURCE_DIR}/deps/IES/build/lib NO_DEFAULT_PATH REQUIRED)
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find_library(libLTStdPlatform NAMES LTStdPlatform PATHS ${PROJECT_SOURCE_DIR}/deps/IES/build/lib NO_DEFAULT_PATH REQUIRED)
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add_library(libFocalPointSDK SHARED IMPORTED)
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add_library(libLTStdPlatform SHARED IMPORTED)
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set_target_properties(libFocalPointSDK PROPERTIES IMPORTED_LOCATION deps/IES/build/lib/libFocalpointSDK.la)
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set_target_properties(libLTStdPlatform PROPERTIES IMPORTED_LOCATION deps/IES/build/lib/libLTStdPlatform.la)
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add_executable(fsmd src/fsmd.cpp src/device/PCIEDevice.cpp src/fm10k/FM10K.cpp src/fm10k/Functions.cpp src/fm10k/Port.cpp src/fm10k/IES.cpp)
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add_executable(fsm src/fsm.cpp)
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2
deps/IES
vendored
2
deps/IES
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@ -1 +1 @@
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Subproject commit 5fa6e3b8bff15be7edea55eea8bee7c17d28b5ca
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Subproject commit 3776b9148f56c026c834476a9990a398b4c64cdb
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@ -77,6 +77,7 @@ std::vector<PCIEDevice::DeviceEntry> PCIEDevice::DeviceEntry::find() {
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if (access((basePath + "/resource4").c_str(), F_OK) == 0) {
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auto vpd = get_file_contents(basePath + "/vpd");
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//auto uevent = get_file_contents(basePath + "/uevent");
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entries.emplace_back(basePath + "/resource4", vendor, _class, vpd);
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}
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}
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@ -1,5 +1,7 @@
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#include "FM10K.h"
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#include "registers/Register.h"
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#include "IES.h"
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#include "device/PCIEDevice.h"
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#include <chrono>
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#include <thread>
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@ -70,6 +72,7 @@ std::string FM10K::FM10K::getHardwareInformationString() const {
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return s;
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}
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/*
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bool FM10K::FM10K::initializationSequence() const {
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if(mapRegister<registers::MGMT::SOFT_RESET>()->fields.ColdReset){
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//Not yet initialized from cold reset
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@ -225,46 +228,6 @@ bool FM10K::FM10K::initializationSequence() const {
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//5.4.3.5 Initialization of Scheduler Polling Schedule
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// The TX and RX schedule must be initialized according to the relative speed of each port.
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/*
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// The example below is 45x10 GbE (36x10 GbE for Ethernet, 5x10 GbE for PEPs (bifurcation mode off), 2 for Tunneling Engines, 1xFIBM and 1x10 GbE for idle).
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// Logical ports 0..35 are physical ports 0..35 (Ethernet)
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for (i=0;i<36;i++)
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{
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SCHED_RX_SCHEDULE[i].Port = i;
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SCHED_RX_SCHEDULE[i].PhysPort = i;
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SCHED_RX_SCHEDULE[i].Quad = 0;
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SCHED_RX_SCHEDULE[i].Idle = 0;
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// Repeat for TX
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SCHED_TX_SCHEDULE[i].Port = i;
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SCHED_TX_SCHEDULE[i].PhysPort = i;
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SCHED_TX_SCHEDULE[i].Quad = 0;
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SCHED_TX_SCHEDULE[i].Idle = 0;
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}
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// Logical ports 36..41,46,47 are 5xPEPs and 2xTE and 1xFIBM (bifurcation ON)
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// (last logical port is mapped to PEP[8]
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int xLogPort[8] = { 36, 37, 38, 39, 40, 41, 46, 47 };
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int xPhysPort[8] = { 36, 40, 44, 48, 52, 56, 60, 63 };
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int xQuad[8] = { 1, 1, 1, 1, 1, 1, 0, 0 };
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for (i=0;i<8;i++)
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{
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SCHED_RX_SCHEDULE[i+36].Port = xLogPort[i];
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SCHED_RX_SCHEDULE[i+36].PhysPort = xPhysPort[i];
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SCHED_RX_SCHEDULE[i+36].Quad = xQuad[i];
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SCHED_RX_SCHEDULE[i+36].Idle = 0;
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// Repeat for TX
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SCHED_TX_SCHEDULE[i+36].Port = xLogPort[i];
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SCHED_TX_SCHEDULE[i+36].PhysPort = xPhysPort[i];
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SCHED_TX_SCHEDULE[i+36].Quad = xQuad[i];
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SCHED_TX_SCHEDULE[i+36].Idle = 0;
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}
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// Start Scheduler
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SCHED_SCHEDULE_CTRL.RxPage = 0;
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SCHED_SCHEDULE_CTRL.RxMaxIndex = 43;
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SCHED_SCHEDULE_CTRL.RxEnable = 1;
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SCHED_SCHEDULE_CTRL.TxPage = 0;
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SCHED_SCHEDULE_CTRL.TxMaxIndex = 43;
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SCHED_SCHEDULE_CTRL.TxEnable = 1;
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*/
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@ -299,6 +262,7 @@ bool FM10K::FM10K::initializationSequence() const {
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return true;
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}
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*/
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bool FM10K::FM10K::isPEPEnabled(uint8_t pep) const {
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return (mapRegister<registers::MGMT::DEVICE_CFG>()->fields.PCIeEnable & (1 << pep)) > 0;
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@ -311,3 +275,21 @@ void FM10K::FM10K::wait(uint32_t microseconds) {
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void FM10K::FM10K::wait_ns(uint32_t nanoseconds) {
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std::this_thread::sleep_for(std::chrono::nanoseconds (nanoseconds));
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}
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bool FM10K::FM10K::initialize() const {
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auto& ies = IES::getInstance();
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if(!ies.loadKnownConfiguration(getHardwareInformationString() + "_AUTO_100G")){
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return false;
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}
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auto pcieDevice = dynamic_cast<PCIEDevice*>(m_device.get());
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if(pcieDevice != nullptr){
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ies.replaceConfigEntry("api.platform.config.switch.0.uioDevName", IES::TlvType::Null, "");
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ies.replaceConfigEntry("api.platform.config.switch.0.resource4DevName", IES::TlvType::Text, pcieDevice->getDeviceEntry().getDevicePath());
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}else{
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return false;
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}
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//TODO UIO support
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return ies.init();
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}
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@ -114,7 +114,7 @@ namespace FM10K{
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return portIndex < m_ports.size() ? &m_ports.back() : nullptr;
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}
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bool initializationSequence() const;
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bool initialize() const;
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bool isPEPEnabled(uint8_t pep) const;
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@ -124,7 +124,6 @@ namespace FM10K{
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std::unique_ptr<Device> m_device;
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HardwareInformation m_hwInfo{};
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std::vector<Port> m_ports;
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void* m_ies = nullptr;
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};
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}
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@ -1,6 +1,8 @@
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#include "IES.h"
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#include <unordered_map>
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#include <sys/param.h>
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#include <fstream>
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#include "IES_SDK.h"
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@ -8,20 +10,17 @@
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namespace FM10K{
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namespace IES_Static{
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static bool IES_INITIALIZED = false;
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static fm_semaphore semaphore;
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static fm_int sw = 0;
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using TlvType = FM10K::IES::TlvType;
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}
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}
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std::unique_ptr<FM10K::IES> FM10K::IES::instance = nullptr;
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bool FM10K::IES::init() {
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if(IES_Static::IES_INITIALIZED){
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if(m_initialized){ //TODO: override
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return true;
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}
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@ -33,6 +32,28 @@ bool FM10K::IES::init() {
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std::abort();
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}*/
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if(!writePlatformConfiguration()){
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std::abort();
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}
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//Override platform configuration for fmInitialize()
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//set FM_LIBERTY_TRAIL_CONFIG_FILE to NVM_NAME ("NVM") to load config from Non-Volatile Memory of FM10K
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//can also set FM_API_ATTR_FILE to override, local_attributes.cfg
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//other env FM_API_SHM_KEY, INSTRUMENT_LOG_FILE
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//it also loads "fm_api_attributes.cfg" by default for current working directory
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if(setenv("FM_LIBERTY_TRAIL_CONFIG_FILE", getPlatformConfigurationPath().c_str(), true) != 0){
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std::abort();
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}
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//Temporarily switch cwd
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char tempcwd[MAXPATHLEN];
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if(getcwd(tempcwd, sizeof(tempcwd)) == nullptr){
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std::abort();
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}
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if(chdir(getTempPath().c_str()) != 0){
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std::abort();
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}
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fmCreateSemaphore("seq", FM_SEM_BINARY, &IES_Static::semaphore, 0);
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if(fmInitialize(eventHandler) != FM_OK){
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@ -47,7 +68,13 @@ bool FM10K::IES::init() {
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std::abort();
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}
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IES_Static::IES_INITIALIZED = true;
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//Restore cwd
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if(chdir(tempcwd) != 0){
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std::abort();
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}
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m_initialized = true;
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return true;
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}
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@ -184,4 +211,43 @@ bool FM10K::IES::loadKnownConfiguration(const std::string &key) {
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return true;
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}
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FM10K::IES::~IES() {
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if(!m_tempPath.empty()){
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remove((m_tempPath + "/fm_platform_attributes.cfg").c_str());
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rmdir(m_tempPath.c_str());
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m_tempPath.clear();
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}
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}
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const std::string &FM10K::IES::getTempPath() {
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if(m_tempPath.empty()){
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const char * const tmplt = "/tmp/fsmd_XXXXXX";
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char buffer[MAXPATHLEN] = {0};
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strncpy(buffer, tmplt, strlen(tmplt));
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if(mkdtemp(buffer) == nullptr){
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std::abort();
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}
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m_tempPath = buffer;
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}
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return m_tempPath;
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}
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bool FM10K::IES::writePlatformConfiguration() {
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std::ofstream f;
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f.open(getPlatformConfigurationPath(), std::ios::out | std::ios::binary | std::ios::trunc);
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if(f.fail()){
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return false;
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}
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f << getPlatformConfiguration();
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f.close();
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return f.fail();
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}
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std::string FM10K::IES::getPlatformConfigurationPath() {
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return getTempPath() + "/fm_platform_attributes.cfg";
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}
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FM10K::IES::IES() = default;
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@ -12,6 +12,7 @@ namespace FM10K {
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class IES {
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public:
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static IES& getInstance();
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~IES();
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bool isInitialized() const{
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return m_initialized;
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@ -40,15 +41,22 @@ namespace FM10K {
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std::string getPlatformConfiguration() const;
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bool writePlatformConfiguration();
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const std::string& getTempPath();
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std::string getPlatformConfigurationPath();
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bool init();
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private:
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IES();
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std::map<std::string, std::pair<TlvType, std::string>> m_configuration{};
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bool m_initialized = false;
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std::string m_tempPath;
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static std::unique_ptr<IES> instance;
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static bool init();
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void handleSwitchInsertedEvent(int sw);
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void handlePortEvent(int sw, struct _fm_eventPort&);
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@ -46,7 +46,7 @@ namespace FM10K {
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{"api.platform.config.switch.0.cpuPort", {TlvType::Integer, "6"}},
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{"api.platform.config.switch.0.bootCfg.mgmtPep", {TlvType::Integer, "6"}},
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{"api.platform.config.switch.0.bootCfg.mgmtPep", {TlvType::Integer, "-1"}},
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{"api.platform.config.switch.0.bootCfg.pep.0.mode", {TlvType::Boolean, "0"}},
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{"api.platform.config.switch.0.bootCfg.pep.2.mode", {TlvType::Boolean, "0"}},
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{"api.platform.config.switch.0.bootCfg.pep.4.mode", {TlvType::Boolean, "0"}},
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@ -58,30 +58,25 @@ namespace FM10K {
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{"api.platform.config.switch.0.bootCfg.pep.6.enable", {TlvType::Boolean, "1"}},
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{"api.platform.config.switch.0.bootCfg.pep.8.enable", {TlvType::Boolean, "0"}},
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{"api.platform.config.switch.0.bootCfg.pep.0.bar4Allowed", {TlvType::Boolean, "1"}},
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{"api.platform.config.switch.0.bootCfg.pep.2.bar4Allowed", {TlvType::Boolean, "1"}},
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{"api.platform.config.switch.0.bootCfg.pep.4.bar4Allowed", {TlvType::Boolean, "1"}},
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{"api.platform.config.switch.0.bootCfg.pep.6.bar4Allowed", {TlvType::Boolean, "1"}},
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{"api.platform.config.switch.0.portIndex.0.portMapping", {TlvType::Text, "\"LOG = 0 PCIE=8\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.0.portMapping",
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{TlvType::Text, "\"LOG=1 EPL=1 LANE=0\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.1.portMapping",
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{TlvType::Text, "\"LOG=1 EPL=1 LANE=1\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.2.portMapping",
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{TlvType::Text, "\"LOG=1 EPL=1 LANE=2\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.3.portMapping",
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{TlvType::Text, "\"LOG=1 EPL=1 LANE=3\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.0.portMapping", {TlvType::Text, "\"LOG=1 EPL=1 LANE=0\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.1.portMapping", {TlvType::Text, "\"LOG=1 EPL=1 LANE=1\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.2.portMapping", {TlvType::Text, "\"LOG=1 EPL=1 LANE=2\""}},
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{"api.platform.config.switch.0.portIndex.1.lane.3.portMapping", {TlvType::Text, "\"LOG=1 EPL=1 LANE=3\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.0.portMapping",
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{TlvType::Text, "\"LOG=2 EPL=7 LANE=0\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.1.portMapping",
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{TlvType::Text, "\"LOG=2 EPL=7 LANE=1\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.2.portMapping",
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{TlvType::Text, "\"LOG=2 EPL=7 LANE=2\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.3.portMapping",
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{TlvType::Text, "\"LOG=2 EPL=7 LANE=3\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.0.portMapping", {TlvType::Text, "\"LOG=2 EPL=7 LANE=0\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.1.portMapping", {TlvType::Text, "\"LOG=2 EPL=7 LANE=1\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.2.portMapping", {TlvType::Text, "\"LOG=2 EPL=7 LANE=2\""}},
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{"api.platform.config.switch.0.portIndex.2.lane.3.portMapping", {TlvType::Text, "\"LOG=2 EPL=7 LANE=3\""}},
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{"api.platform.config.switch.0.portIndex.3.portMapping", {TlvType::Text, "\"LOG=3 PCIE=0\""}},
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@ -96,15 +91,17 @@ namespace FM10K {
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{"api.platform.config.switch.0.portIndex.2.interfaceType", {TlvType::Text, "QSFP_LANE0"}},
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{"api.platform.config.switch.0.portIndex.1.speed", {TlvType::Integer, SPEED_100G}},
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{"api.platform.config.switch.0.portIndex.0.speed", {TlvType::Integer, SPEED_10G}},
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{"api.platform.config.switch.0.portIndex.1.speed", {TlvType::Integer, SPEED_100G}},
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{"api.platform.config.switch.0.portIndex.2.speed", {TlvType::Integer, SPEED_100G}},
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{"api.platform.config.switch.0.portIndex.3.speed", {TlvType::Integer, SPEED_50G}},
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{"api.platform.config.switch.0.portIndex.4.speed", {TlvType::Integer, SPEED_50G}},
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{"api.platform.config.switch.0.portIndex.5.speed", {TlvType::Integer, SPEED_50G}},
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{"api.platform.config.switch.0.portIndex.6.speed", {TlvType::Integer, SPEED_50G}},
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{"api.platform.config.switch.0.portIndex.5.speed", {TlvType::Integer, SPEED_50G}}, //? second PCIe group
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{"api.platform.config.switch.0.portIndex.6.speed", {TlvType::Integer, SPEED_50G}}, //? second PCIe group
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|
||||
{"api.platform.config.switch.0.portIndex.2.speed", {TlvType::Integer, SPEED_100G}},
|
||||
|
||||
{"api.platform.config.switch.0.port.default.ethernetMode", {TlvType::Text, "DISABLED"}},
|
||||
|
||||
|
@ -115,11 +112,8 @@ namespace FM10K {
|
|||
|
||||
{"api.platform.config.switch.0.port.default.capability", {TlvType::Text, "NONE"}},
|
||||
|
||||
|
||||
{"api.platform.config.switch.0.portIndex.1.capability",
|
||||
{TlvType::Text, "LAG,ROUTE,10G,25G,40G,100G,SW_LED"}},
|
||||
{"api.platform.config.switch.0.portIndex.2.capability",
|
||||
{TlvType::Text, "LAG,ROUTE,10G,25G,40G,100G,SW_LED"}},
|
||||
{"api.platform.config.switch.0.portIndex.1.capability",{TlvType::Text, "LAG,ROUTE,10G,25G,40G,100G,SW_LED"}},
|
||||
{"api.platform.config.switch.0.portIndex.2.capability", {TlvType::Text, "LAG,ROUTE,10G,25G,40G,100G,SW_LED"}},
|
||||
|
||||
|
||||
{"api.platform.config.switch.0.port.default.lanePolarity", {TlvType::Text, "INVERT_NONE"}},
|
||||
|
@ -131,8 +125,7 @@ namespace FM10K {
|
|||
{"api.platform.config.switch.0.sharedLibraryName", {TlvType::Text, "libLTStdPlatform.so"}},
|
||||
|
||||
|
||||
{"api.platform.config.switch.0.sharedLibrary.disable",
|
||||
{TlvType::Text, "GetPortIntrPending,EnablePortIntr"}},
|
||||
{"api.platform.config.switch.0.sharedLibrary.disable", {TlvType::Text, "GetPortIntrPending,EnablePortIntr"}},
|
||||
|
||||
|
||||
{"api.platform.lib.config.bus0.i2cDevName", {TlvType::Text, "switchI2C"}},
|
||||
|
@ -197,34 +190,43 @@ namespace FM10K {
|
|||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.index", {TlvType::Integer, "2"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.0.pcaIo.pin", {TlvType::Integer, "0"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.1.pcaIo.pin", {TlvType::Integer, "1"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.1.pcaIo.usage", {TlvType::Text, "LINK,40G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.2.pcaIo.pin", {TlvType::Integer, "2"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.2.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.3.pcaIo.pin", {TlvType::Integer, "3"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.3.pcaIo.usage",
|
||||
{TlvType::Text, "LINK,100G"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.0.3.pcaIo.usage",{TlvType::Text, "LINK,100G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.pcaIo.index", {TlvType::Integer, "2"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.0.pcaIo.pin", {TlvType::Integer, "4"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.1.pcaIo.pin", {TlvType::Integer, "5"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.1.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.pcaIo.index", {TlvType::Integer, "2"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.0.pcaIo.pin", {TlvType::Integer, "6"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.1.pcaIo.pin", {TlvType::Integer, "7"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.2.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.pcaIo.index", {TlvType::Integer, "4"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.0.pcaIo.pin", {TlvType::Integer, "0"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.1.pcaIo.pin", {TlvType::Integer, "1"}},
|
||||
{"api.platform.lib.config.hwResourceId.0.portLed.3.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
|
@ -245,33 +247,43 @@ namespace FM10K {
|
|||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.index", {TlvType::Integer, "5"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.0.pcaIo.pin", {TlvType::Integer, "0"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.1.pcaIo.pin", {TlvType::Integer, "1"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.1.pcaIo.usage", {TlvType::Text, "LINK,40G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.2.pcaIo.pin", {TlvType::Integer, "2"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.2.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.3.pcaIo.pin", {TlvType::Integer, "3"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.0.3.pcaIo.usage", {TlvType::Text, "LINK,100G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.pcaIo.index", {TlvType::Integer, "5"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.0.pcaIo.pin", {TlvType::Integer, "4"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.1.pcaIo.pin", {TlvType::Integer, "5"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.1.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.pcaIo.index", {TlvType::Integer, "5"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.0.pcaIo.pin", {TlvType::Integer, "6"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.1.pcaIo.pin", {TlvType::Integer, "7"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.2.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.type", {TlvType::Text, "PCA"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.pcaIo.index", {TlvType::Integer, "4"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.0.pcaIo.pin", {TlvType::Integer, "2"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.0.pcaIo.usage", {TlvType::Text, "LINK,10G"}},
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.1.pcaIo.pin", {TlvType::Integer, "3"}},
|
||||
{"api.platform.lib.config.hwResourceId.1.portLed.3.1.pcaIo.usage", {TlvType::Text, "LINK,25G"}},
|
||||
|
||||
|
@ -284,6 +296,8 @@ namespace FM10K {
|
|||
{"api.platform.lib.config.hwResourceId.2.vrm.pcaMux.value", {TlvType::Integer, "0x04"}},
|
||||
|
||||
{"api.platform.config.switch.0.VDDS.hwResourceId", {TlvType::Integer, "2"}},
|
||||
|
||||
|
||||
{"api.platform.lib.config.hwResourceId.3.type", {TlvType::Text, "VRM"}},
|
||||
{"api.platform.lib.config.hwResourceId.3.vrm.busSelType", {TlvType::Text, "PCAMUX"}},
|
||||
{"api.platform.lib.config.hwResourceId.3.vrm.bus", {TlvType::Integer, "0"}},
|
||||
|
|
|
@ -43,7 +43,7 @@ int main() {
|
|||
port.m_portType = Port::PortType::EPL;
|
||||
port.m_interfaceType = Port::InterfaceType::QSFP_LANE0;
|
||||
|
||||
if(fm10k.initializationSequence()){
|
||||
if(fm10k.initialize()){
|
||||
std::cout << "success" << std::endl;
|
||||
}else{
|
||||
std::cout << "fail" << std::endl;
|
||||
|
|
Loading…
Reference in a new issue