WIP: added unhardcoded setClockOutDiv FASTCALL, init_PCIE_EACH_SERDES_SPICO loop

src/clocking.asm

@@ -57,8 +57,20 @@ init_startClocks:
     WAIT                    10
     RET
 
-init_PCIE_setClockDivTo50:
-    SET PLL_PCIE_CTRL, 0x280000, 0xfc0000 ; Set OutDiv = 50
+
+; FASTCALL void (uint OutDiv)
+init_PCIE_setClockOutDiv:
+    SHL R0, P0, 18 ; P0 << 18
+    AND R0, R0, 0x00fc0000
+
+    MOV R1, PLL_PCIE_CTRL
+    AND R1, R1, 0xff03ffff
+
+    OR R1, R1, R0
+    ; PLL_PCIE_CTRL = (PLL_PCIE_CTRL & 0xff03ffff) | ((P0 << 18) & 0x00fc0000);
+
+
+    MOV PLL_PCIE_CTRL, R1 ; Set OutDiv
     SET PLL_PCIE_STAT, 0x40, 0x40 ; Value & Mask, set MiscCtrl, "Fast Calibration Mode" = 0, "Asynchronous load signal for PLL output divider." = 1
     SET PLL_PCIE_STAT, 0x00, 0x40 ; Value & Mask, set MiscCtrl all 0 (?)
     RET

src/entrypoint.asm

@@ -38,7 +38,7 @@ entrypoint:
         SET SOFT_RESET, 0, 0x6 ; Enable areas, EPLReset = 0, SwitchReset = 0
         WAIT 10 ; Wait 100ns, minimum
         FASTCALL @init_setPciePEPEnabled, bootCfg_pep0_enable, bootCfg_pep1_enable, bootCfg_pep2_enable, bootCfg_pep3_enable, bootCfg_pep4_enable, bootCfg_pep5_enable, bootCfg_pep6_enable, bootCfg_pep7_enable, bootCfg_pep8_enable
-        CALL @init_PCIE_setClockDivTo50
+        FASTCALL @init_PCIE_setClockOutDiv, 10
 
         CALL @lock_PCIE_SBUS_take ; Try to take lock for ourselves
         BNE RRET, 1, 0x1, @.skipPcieInit ; We failed to take the lock
@@ -46,8 +46,21 @@ entrypoint:
         CALL @init_PCIE_MASTER_SPICO
         BNE RRET, 1, 0x1, @.skipPcieInit ; Failed to init properly
 
-        CALL @init_PCIE_SERDES_SPICO
+        CALL @init_ALL_PCIE_SERDES_SPICO
         BNE RRET, 1, 0x1, @.skipPcieInit ; Failed to init properly
+
+        ; Restart PEPs
+        MOV api_BSM_STATUS, 0x00000010
+        FASTCALL @init_setPciePEPEnabled, bootCfg_pep0_enable, bootCfg_pep1_enable, bootCfg_pep2_enable, bootCfg_pep3_enable, bootCfg_pep4_enable, bootCfg_pep5_enable, bootCfg_pep6_enable, bootCfg_pep7_enable, bootCfg_pep8_enable
+        WAIT 5
+        MOV api_BSM_STATUS, 0x00010010
+        MOV api_PCIE_DE_WARM_RESET_STATUS, api_BSM_STATUS
+
+        FASTCALL @init_PCIE_setClockOutDiv, 6
+
+        CALL @init_PCIE_EACH_SERDES_SPICO
+        BNE RRET, 1, 0x1, @.skipPcieInit ; Failed to init properly
+
         ; TODO complete this
 
 

src/pcie.asm

@@ -193,7 +193,7 @@ init_PCIE_MASTER_SPICO:
     MOV api_PCIE_MASTER_STATUS, 1
     RET
 
-init_PCIE_SERDES_SPICO:
+init_ALL_PCIE_SERDES_SPICO:
     MOV api_PCIE_SERDES_STATUS, 0
 
     MOV R0, 0 ; Why, this must be a constant!
@@ -246,6 +246,7 @@ init_PCIE_SERDES_SPICO:
     .skipFullLock: ; (??)
     MOV api_SERDES_FW_VERSION, plaftorm_SERDES_FW_VERSION
 
+    ; TODO: move this to its own call
     MOV R3, 1 ; Why, this must be a constant!. Also registered loc_089110_load_config_unknown_1 on original code
     BEQ R3, 0, 0x1, @.successCommand ; Skip CRC and version checks
         MOV api_BSM_STATUS, 0x0004000e
@@ -383,3 +384,83 @@ init_PCIE_SERDES_SPICO:
     MOV api_PCIE_SERDES_FW_DL_STATUS, api_BSM_STATUS
     MOV api_PCIE_SERDES_STATUS, 1
     RET
+
+
+init_PCIE_EACH_SERDES_SPICO:
+    MOV api_BSM_STATUS, 0x0000000f
+
+    MOV R0, 2 ; Current SERDES device index
+    MOV R1, 0x00e00ff0 ; Current data to write
+
+    .do:
+        FASTCALL @execute_SBus_PCIE_Command, 0xfd, R0, 0, R1 ; Execute command
+        BNE RRET, 1, 0x1, @.failCommand ; Command failed
+        ADD R0, R0, 2 ; Increase index for next spico
+
+        .check0: BNE, R0, 0x0a, 0xFFFFFFFF, @.check1
+            BEQ DEVICE_CFG, 0, 0x01, @.check1 ; PEP0 is 8x8x
+                MOV R1, 0x00e10ff0
+        .check1: BNE, R0, 0x12, 0xFFFFFFFF, @.check2
+            MOV R1, 0x00e20ff0
+
+        .check2: BNE, R0, 0x1a, 0xFFFFFFFF, @.check3
+            BEQ DEVICE_CFG, 0, 0x02, @.check3 ; PEP2 is 8x8x
+                MOV R1, 0x00e30ff0
+        .check3: BNE, R0, 0x22, 0xFFFFFFFF, @.check4
+            MOV R1, 0x00e40ff0
+
+        .check4: BNE, R0, 0x3a, 0xFFFFFFFF, @.check5
+            BEQ DEVICE_CFG, 0, 0x04, @.check5 ; PEP4 is 8x8x
+                MOV R1, 0x00e50ff0
+        .check5: BNE, R0, 0x32, 0xFFFFFFFF, @.check6
+            MOV R1, 0x00e60ff0
+
+        .check6: BNE, R0, 0x4a, 0xFFFFFFFF, @.continue
+            BEQ DEVICE_CFG, 0, 0x08, @.continue ; PEP6 is 8x8x
+                MOV R1, 0x00e70ff0
+        .continue:
+    BNE R0, platform_SERDES_SPICO_COUNT, 0xFFFFFFFF, @.do
+
+    MOV R0, 3 ; Current SERDES device index, odd
+    MOV R1, 0x000000d0 ; Current data to write
+    .do2:
+        FASTCALL @execute_SBus_PCIE_Command, 0x24, R0, 0, R1 ; Execute command
+        BNE RRET, 1, 0x1, @.failCommand ; Command failed
+        ADD R0, R0, 2 ; Increase index for next spico
+
+        .check20: BNE, R0, 0x0b, 0xFFFFFFFF, @.check21
+            BEQ DEVICE_CFG, 0, 0x01, @.check21 ; PEP0 is 8x8x
+                MOV R1, 0x000000d1
+        .check21: BNE, R0, 0x13, 0xFFFFFFFF, @.check22
+            MOV R1, 0x000000d2
+
+        .check22: BNE, R0, 0x1b, 0xFFFFFFFF, @.check23
+            BEQ DEVICE_CFG, 0, 0x02, @.check23 ; PEP2 is 8x8x
+                MOV R1, 0x000000d3
+        .check23: BNE, R0, 0x23, 0xFFFFFFFF, @.check24
+            MOV R1, 0x000000d4
+
+        .check24: BNE, R0, 0x3b, 0xFFFFFFFF, @.check25
+            BEQ DEVICE_CFG, 0, 0x04, @.check25 ; PEP4 is 8x8x
+                MOV R1, 0x000000d5
+        .check25: BNE, R0, 0x33, 0xFFFFFFFF, @.check26
+            MOV R1, 0x000000d6
+
+        .check26: BNE, R0, 0x4b, 0xFFFFFFFF, @.continue2
+            BEQ DEVICE_CFG, 0, 0x08, @.continue2 ; PEP6 is 8x8x
+                MOV R1, 0x000000d7
+        .continue2:
+    BNE R0, platform_SERDES_SPICO_COUNT +1, 0xFFFFFFFF, @.do2
+
+    MOV RRET, 1 ; Success
+    MOV api_SERDES_OOR_STATUS_PASS_1, 0
+    MOV api_SW_LOCK_ERR_STATUS, 0
+    MOV api_BSM_STATUS, 0x0004000f
+    MOV api_PCIE_SERDES_INIT_STATUS, api_BSM_STATUS
+    RET
+    .failCommand:
+    MOV RRET, 0 ; Failure
+    SET api_BSM_STATUS, 0x0000fff0, 0x0000fff0
+    MOV api_PCIE_SERDES_INIT_STATUS, api_BSM_STATUS
+    MOV api_PCIE_SERDES_STATUS, 0x00000001
+    RET