WIP: interrupt handling, use PUSH / new stack system
This commit is contained in:
parent
cd97cfff81
commit
18c5d31cc2
1
Makefile
1
Makefile
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@ -10,6 +10,7 @@ firmware.bin: src/rrc-as src/entrypoint.asm
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config.asm src/platform.asm \
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blobs/master_spico_fw.asm blobs/serdes_spico_fw.asm \
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src/entrypoint.asm \
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src/interrupt.asm \
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src/clocking.asm \
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src/pcie.asm \
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firmware.bin
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@ -23,9 +23,6 @@
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.constant rrcc_SPI_TRANSFER_MODE, bootCfg_spiTransferMode
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.constant rrcc_SPI_TRANSFER_SPEED, bootCfg_spiTransferSpeed
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.constant rrcc_IMAGE_VERSION, platform_firmware_versionNumber
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entrypoint:
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CALL @init_startClocks
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@ -88,11 +85,11 @@ entrypoint:
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SHL R1, R1, 6 ; R1 << 3
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SHL R1, R1, 24 ; R1 << 24
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OR R0, R0, R1
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MOV BSM_ARGS, R0 ; Configure base address, mode and speed for interrupt handler
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MOV BSM_ARGS, R0 ; Configure base address, mode and speed for interrupt handler (for PCIE_IP.VPD_Request, or When there is a global interrupt directed to the BSM (i.e. |(GLOBAL_INTERRUPT_DETECT & ~INTERRUPT_MASK_BSM) is true) and BSM_CTRL.Command is set to NONE.)
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; Setup Interrupt from PEP Mask to Boot State Machine configuration
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MOV R1, BSM_ADDR_OFFSET_2 ; Save any old offset
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MOV BSM_ADDR_OFFSET_2, 0x000000 ; PCIe base address for PEP
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MOV R1, BSM_ADDR_OFFSET_1 ; Save any old offset
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MOV BSM_ADDR_OFFSET_1, 0x000000 ; PCIe base address for PEP
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MOV R0, 0x000007ff ; PCIE_IB settings, All enabled
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SET R0, 0x00000000, 0x00000008 ; Mask PCIE_IP.VPD_Request = 0
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@ -103,60 +100,60 @@ entrypoint:
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; TODO: move this to pcie.asm and make it a function
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BNE DEVICE_CFG, 0x00000080, 0x00000080, @.skip_PEP0_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00002000, 0x00002000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00002000 ; Set PEP PCIeActive = 0
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.skip_PEP0_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP0_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x0080, 0x0080, @.skip_PEP1_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00004000, 0x00004000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00004000 ; Set PEP PCIeActive = 0
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.skip_PEP1_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP1_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00000100, 0x00000100, @.skip_PEP2_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00008000, 0x00008000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00008000 ; Set PEP PCIeActive = 0
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.skip_PEP2_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP2_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00000200, 0x00000200, @.skip_PEP3_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00010000, 0x00010000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00010000 ; Set PEP PCIeActive = 0
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.skip_PEP3_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP3_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00000400, 0x00000400, @.skip_PEP4_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00020000, 0x00020000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00020000 ; Set PEP PCIeActive = 0
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.skip_PEP4_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP4_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00000800, 0x00000800, @.skip_PEP5_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00040000, 0x00040000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00040000 ; Set PEP PCIeActive = 0
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.skip_PEP5_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP5_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00001000, 0x00001000, @.skip_PEP6_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00080000, 0x00080000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00080000 ; Set PEP PCIeActive = 0
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.skip_PEP6_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP6_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00002000, 0x00002000, @.skip_PEP7_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00100000, 0x00100000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00100000 ; Set PEP PCIeActive = 0
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.skip_PEP7_masking: ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
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.skip_PEP7_masking: ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
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BNE DEVICE_CFG, 0x00004000, 0x00004000, @.skip_PEP8_masking; Is PCIeEnable != 1
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SET SOFT_RESET 0x00200000, 0x00200000 ; Set PEP PCIeActive = 1
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MOV~20 PCIE_IB, R0 ; Copy interrupt settings
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MOV~10 PCIE_IB, R0 ; Copy interrupt settings
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SET SOFT_RESET 0x00000000, 0x00200000 ; Set PEP PCIeActive = 0
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.skip_PEP8_masking:
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MOV BSM_ADDR_OFFSET_2, R1 ; Restore old offset
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MOV BSM_ADDR_OFFSET_1, R1 ; Restore old offset
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CALL @init_finishClockConfig
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@ -169,10 +166,6 @@ entrypoint:
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MOV api_EEPROM_IMAGE_VERSION, platform_firmware_versionNumber ; Sets the version on memory where a switch manager can read it
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RET
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interrupt_handler:
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; TODO implement this
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END
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init_markSbusBooted:
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MOV api_BSM_STATUS, 0x0000b
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MOV SBUS_EPL_CFG, 0 ; Set SBUS_ControllerReset = 0 (Not in reset)
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187
src/interrupt.asm
Normal file
187
src/interrupt.asm
Normal file
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@ -0,0 +1,187 @@
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; Copyright (c) 2021, rrc-open-firmware FM10K-Documentation Contributors
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; * Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; * Neither the name of the copyright holder nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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interrupt_handler:
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MOV api_BSM_STATUS, 0x000f0011
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WRITE rrcc_STACK_POINTER, rrcc_STACK_START ; Reset Stack pointer to its starting position
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WRITE R0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ; Zero R0 - RF
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WRITE api_RE_RESET_MASK_STATUS_1, 0x00000000, 0x00000000 ; 64-bit write
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.takeSoftResetLock: CALL @lock_soft_reset_take
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BNE RRET, 1, 0x1, @.takeSoftResetLock ; Failed to take lock, keep retrying in busy loop
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CALL @interrupt_handle_each_source
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; TODO this
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END
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lock_soft_reset_take:
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PNE api_SOFT_RESET_LOCK_STATE, 0, 0x3, 20000, 50, @.failTakeLock
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SET api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_NVM, 0x3
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BNE api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_NVM, 0x3, @.retryLock
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MOV RRET, 1 ; Success
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RET
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.retryLock:
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PNE api_SOFT_RESET_LOCK_STATE, 0, 0x3, 20000, 50, @.failTakeLock
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SET api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_NVM, 0x3
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BNE api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_NVM, 0x3, @.failTakeLock
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MOV RRET, 1 ; Success
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RET
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.failTakeLock:
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MOV RRET, 0 ; Failure
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SET api_SW_LOCK_ERR_STATUS, 0x00000100, 0x00000100
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BEQ api_SW_LOCK_ERR_STATUS, 0xfe00, 0xfe00, @.returnFail
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ADD api_SW_LOCK_ERR_STATUS, api_SW_LOCK_ERR_STATUS, 0x200
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RET
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.returnFail: SET api_SW_LOCK_ERR_STATUS, 0x0000, 0xfe00
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ADD api_SW_LOCK_ERR_STATUS, api_SW_LOCK_ERR_STATUS, 0x200
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RET
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lock_soft_reset_release:
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BNE api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_NVM, 0x3, @.return ; If we hold the lock
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SET api_SOFT_RESET_LOCK_STATE, platform_SOFT_RESET_LOCK_FREE, 0x3 ; Release lock
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.return:
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RET
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interrupt_handle_each_source:
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BNE GLOBAL_INTERRUPT_DETECT_0, 0x00000001, 0x00000001, @.skipPep0 ; Need to handle PEP 0
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MOV api_BSM_STATUS, 0x00000011
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CALL @interrupt_set_clocks_once_PEP0
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.skipPep0:
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RET
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.constant tmp_PEP_CLK_MASK 0x00700000
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.constant tmp_PEP_STAT_MASK 0x00000100
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.constant tmp_PEP_RESET_MASK 0x00000010
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.constant tmp_PEP_ACTIVE_MASK 0x00002000
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interrupt_set_clocks_once_PEP0:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP0_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_RESET_MASK 0x00000020
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.constant tmp_PEP_ACTIVE_MASK 0x00004000
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interrupt_set_clocks_once_PEP1:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP1_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_CLK_MASK 0x03800000
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.constant tmp_PEP_STAT_MASK 0x00000200
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.constant tmp_PEP_RESET_MASK 0x00000040
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.constant tmp_PEP_ACTIVE_MASK 0x00008000
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interrupt_set_clocks_once_PEP2:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP2_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_RESET_MASK 0x00000080
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.constant tmp_PEP_ACTIVE_MASK 0x00010000
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interrupt_set_clocks_once_PEP3:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP3_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_CLK_MASK 0x1c000000
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.constant tmp_PEP_STAT_MASK 0x00000400
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.constant tmp_PEP_RESET_MASK 0x00000100
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.constant tmp_PEP_ACTIVE_MASK 0x00020000
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interrupt_set_clocks_once_PEP4:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP4_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_RESET_MASK 0x00000200
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.constant tmp_PEP_ACTIVE_MASK 0x00040000
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interrupt_set_clocks_once_PEP5:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP5_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_CLK_MASK 0xe0000000
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.constant tmp_PEP_STAT_MASK 0x00000800
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.constant tmp_PEP_RESET_MASK 0x00000400
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.constant tmp_PEP_ACTIVE_MASK 0x00080000
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interrupt_set_clocks_once_PEP6:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
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BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
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AND platform_PEP6_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
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SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
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SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
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SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
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.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
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RET
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.constant tmp_PEP_RESET_MASK 0x00000800
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.constant tmp_PEP_ACTIVE_MASK 0x00100000
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interrupt_set_clocks_once_PEP7:
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BEQ CHIP_VERSION, 0x00, 0x7f, @.skipReset
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BEQ PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
|
||||
BNE PCIE_CLK_STAT, 0x00000000, tmp_PEP_STAT_MASK, @.skipReset ; If RefclkSel != 0
|
||||
AND platform_PEP7_PCIE_CLK_CTRL, PCIE_CLK_CTRL, tmp_PEP_CLK_MASK
|
||||
SET SOFT_RESET, tmp_PEP_RESET_MASK, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 1
|
||||
SET PCIE_CLK_CTRL, 0x00000000, tmp_PEP_CLK_MASK; Set Mode for PEP group = PCIE_REFCLK
|
||||
SET SOFT_RESET, 0x00000000, tmp_PEP_RESET_MASK ; Set PCIeReset for PEP = 0
|
||||
.skipReset: SET SOFT_RESET, tmp_PEP_ACTIVE_MASK, tmp_PEP_ACTIVE_MASK ; Set PCIeActive for PEP = 1
|
||||
RET
|
||||
80
src/pcie.asm
80
src/pcie.asm
|
|
@ -35,11 +35,11 @@ init_setPcieSplitMode:
|
|||
SET DEVICE_CFG, 0x2, 0x2 ; Set PCIeMode[1] = 1 (4x4x4x4)
|
||||
.continue2:
|
||||
|
||||
BEQ~3 P2, 0, 0x1, @.continue4 ; access POPP 1 PEP4
|
||||
BEQ~2 P2, 0, 0x1, @.continue4 ; access POPP 1 PEP4
|
||||
SET DEVICE_CFG, 0x4, 0x4 ; Set PCIeMode[2] = 1 (4x4x4x4)
|
||||
.continue4:
|
||||
|
||||
BEQ~3 P3, 0, 0x1, @.continue6 ; access POPP 2 PEP6
|
||||
BEQ~2 P3, 0, 0x1, @.continue6 ; access POPP 2 PEP6
|
||||
SET DEVICE_CFG, 0x8, 0x8 ; Set PCIeMode[3] = 1 (4x4x4x4)
|
||||
.continue6:
|
||||
RET
|
||||
|
|
@ -54,31 +54,31 @@ init_setPciePEPEnabled:
|
|||
SET DEVICE_CFG, 0, 0x0100 ; Set PCIEnable[1] = 0, default 1
|
||||
.continue1:
|
||||
|
||||
BEQ~3 P2, 1, 0x1, @.continue2 ; PEP2
|
||||
BEQ~2 P2, 1, 0x1, @.continue2 ; PEP2
|
||||
SET DEVICE_CFG, 0, 0x0200 ; Set PCIEnable[2] = 0, default 1
|
||||
.continue2:
|
||||
|
||||
BEQ~3 P3, 1, 0x1, @.continue3 ; PEP3
|
||||
BEQ~2 P3, 1, 0x1, @.continue3 ; PEP3
|
||||
SET DEVICE_CFG, 0, 0x0400 ; Set PCIEnable[3] = 0, default 1
|
||||
.continue3:
|
||||
|
||||
BEQ~3 P4, 1, 0x1, @.continue4 ; PEP4
|
||||
BEQ~2 P4, 1, 0x1, @.continue4 ; PEP4
|
||||
SET DEVICE_CFG, 0, 0x0800 ; Set PCIEnable[4] = 0, default 1
|
||||
.continue4:
|
||||
|
||||
BEQ~3 P5, 1, 0x1, @.continue5 ; PEP5
|
||||
BEQ~2 P5, 1, 0x1, @.continue5 ; PEP5
|
||||
SET DEVICE_CFG, 0, 0x1000 ; Set PCIEnable[5] = 0, default 1
|
||||
.continue5:
|
||||
|
||||
BEQ~3 P6, 1, 0x1, @.continue6 ; PEP6
|
||||
BEQ~2 P6, 1, 0x1, @.continue6 ; PEP6
|
||||
SET DEVICE_CFG, 0, 0x2000 ; Set PCIEnable[6] = 0, default 1
|
||||
.continue6:
|
||||
|
||||
BEQ~3 P7, 1, 0x1, @.continue7 ; PEP7
|
||||
BEQ~2 P7, 1, 0x1, @.continue7 ; PEP7
|
||||
SET DEVICE_CFG, 0, 0x4000 ; Set PCIEnable[7] = 0, default 1
|
||||
.continue7:
|
||||
|
||||
BEQ~3 P8, 1, 0x1, @.continue8 ; PEP8
|
||||
BEQ~2 P8, 1, 0x1, @.continue8 ; PEP8
|
||||
SET DEVICE_CFG, 0, 0x8000 ; Set PCIEnable[8] = 0, default 1
|
||||
.continue8:
|
||||
|
||||
|
|
@ -146,12 +146,12 @@ lock_PCIE_SBUS_release:
|
|||
; }
|
||||
;
|
||||
execute_SBus_PCIE_Command:
|
||||
MOV~03 SBUS_PCIE_REQUEST, P3 ; Set commandData into the request
|
||||
GET SBUS_PCIE_REQUEST, P3 ; Set commandData into the request
|
||||
SHL R0, P1, 8 ; P1 << 8
|
||||
AND R0, R0, 0xff00
|
||||
OR R0, R0, P0 ; Combine (DeviceAddress << 8) | Register
|
||||
|
||||
BEQ~3 P2, 1, 0x1, @.doRead ; Check if we are doing a write or read op
|
||||
BEQ~2 P2, 1, 0x1, @.doRead ; Check if we are doing a write or read op
|
||||
; Do write
|
||||
SET R0, 0x210000, 0xff0000 ; Set WRITE Op 0x21
|
||||
MOV R1, 0x04000000 ; Success value for write ResultCode
|
||||
|
|
@ -505,87 +505,87 @@ init_PCIE_SERDES_PCS_config:
|
|||
MOV R0, 1
|
||||
.skipSetting1toR0:
|
||||
|
||||
MOV R2, BSM_ADDR_OFFSET_2 ; Save offset 2
|
||||
MOV R2, BSM_ADDR_OFFSET_1 ; Save offset 2
|
||||
|
||||
MOV BSM_ADDR_OFFSET_2, 0x000000 ; PCIe base address for PEP
|
||||
MOV BSM_ADDR_OFFSET_1, 0x000000 ; PCIe base address for PEP
|
||||
|
||||
|
||||
BEQ~3, P2, 0, 0x1, @.skip_PEP0_init ; Get PEP0 parameter
|
||||
BEQ~2, P2, 0, 0x1, @.skip_PEP0_init ; Get PEP0 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_a
|
||||
BEQ DEVICE_CFG, 0x1, 0x1, @.skip_PEP0_init
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP0_init:
|
||||
SET api_BSM_STATUS, 0x00100000, 0x00100000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
BEQ~3, P3, 0, 0x1, @.skip_PEP1_init ; Get PEP1 parameter
|
||||
BEQ~2, P3, 0, 0x1, @.skip_PEP1_init ; Get PEP1 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP1_init:
|
||||
SET api_BSM_STATUS, 0x00200000, 0x00200000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
|
||||
BEQ~3, P4, 0, 0x1, @.skip_PEP2_init ; Get PEP2 parameter
|
||||
BEQ~2, P4, 0, 0x1, @.skip_PEP2_init ; Get PEP2 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_a
|
||||
BEQ DEVICE_CFG, 0x2, 0x2, @.skip_PEP2_init
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP2_init:
|
||||
SET api_BSM_STATUS, 0x00400000, 0x00400000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
BEQ~3, P5, 0, 0x1, @.skip_PEP3_init ; Get PEP3 parameter
|
||||
BEQ~2, P5, 0, 0x1, @.skip_PEP3_init ; Get PEP3 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP3_init:
|
||||
SET api_BSM_STATUS, 0x00800000, 0x00800000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
|
||||
BEQ~3, P6, 0, 0x1, @.skip_PEP4_init ; Get PEP4 parameter
|
||||
BEQ~2, P6, 0, 0x1, @.skip_PEP4_init ; Get PEP4 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_a
|
||||
BEQ DEVICE_CFG, 0x4, 0x4, @.skip_PEP4_init
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP4_init:
|
||||
SET api_BSM_STATUS, 0x01000000, 0x01000000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
BEQ~3, P7, 0, 0x1, @.skip_PEP5_init ; Get PEP5 parameter
|
||||
BEQ~2, P7, 0, 0x1, @.skip_PEP5_init ; Get PEP5 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP5_init:
|
||||
SET api_BSM_STATUS, 0x02000000, 0x02000000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
|
||||
BEQ~3, P8, 0, 0x1, @.skip_PEP6_init ; Get PEP6 parameter
|
||||
BEQ~2, P8, 0, 0x1, @.skip_PEP6_init ; Get PEP6 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_a
|
||||
BEQ DEVICE_CFG, 0x8, 0x8, @.skip_PEP6_init
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP6_init:
|
||||
SET api_BSM_STATUS, 0x04000000, 0x04000000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
BEQ~3, P9, 0, 0x1, @.skip_PEP7_init ; Get PEP7 parameter
|
||||
BEQ~2, P9, 0, 0x1, @.skip_PEP7_init ; Get PEP7 parameter
|
||||
CALL @._init_PCIE_SERDES_PCS_config_doRegisterWrites_b
|
||||
.skip_PEP7_init:
|
||||
SET api_BSM_STATUS, 0x08000000, 0x08000000
|
||||
ADD BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_2, 0x100000
|
||||
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
|
||||
|
||||
BEQ~3, P10, 0, 0x1, @.skip_PEP8_init ; Get PEP8 parameter
|
||||
COPY~20, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
|
||||
BEQ~2, P10, 0, 0x1, @.skip_PEP8_init ; Get PEP8 parameter
|
||||
COPY~10, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
|
||||
.skip_PEP8_init:
|
||||
SET api_BSM_STATUS, 0x10000000, 0x10000000
|
||||
|
||||
|
||||
MOV BSM_ADDR_OFFSET_2, R2 ; Restore offset 2
|
||||
MOV BSM_ADDR_OFFSET_1, R2 ; Restore offset 1
|
||||
RET
|
||||
._init_PCIE_SERDES_PCS_config_doRegisterWrites_a:
|
||||
COPY~20, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_1, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_2, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_3, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_1, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_2, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_3, R0, 2 ; Copy two words
|
||||
RET
|
||||
._init_PCIE_SERDES_PCS_config_doRegisterWrites_b:
|
||||
COPY~20, PCIE_SERDES_CTRL_4, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_5, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_6, R0, 2 ; Copy two words
|
||||
COPY~20, PCIE_SERDES_CTRL_7, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_4, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_5, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_6, R0, 2 ; Copy two words
|
||||
COPY~10, PCIE_SERDES_CTRL_7, R0, 2 ; Copy two words
|
||||
RET
|
||||
|
|
@ -30,6 +30,10 @@
|
|||
.constant platform_PCIE_SBUS_LOCK_NVM 1
|
||||
.constant platform_PCIE_SBUS_LOCK_API 2
|
||||
|
||||
.constant platform_SOFT_RESET_LOCK_FREE 0
|
||||
.constant platform_SOFT_RESET_LOCK_NVM 1
|
||||
.constant platform_SOFT_RESET_LOCK_API 2
|
||||
|
||||
.constant platform_SERDES_SPICO_COUNT 0x42
|
||||
.constant platform_PCIE_RMON0_DEVICE_ADDRESS 1
|
||||
; Here go PCIe Lane 0-66 even 0xFF bcast, and PCIe lane PCS 3-67 odd 0xF7 bcast
|
||||
|
|
@ -42,8 +46,20 @@
|
|||
|
||||
|
||||
; Change this?
|
||||
.constant platform_PCIE_SBUS_LOCK_HOLD BSM_SCRATCH_START +0x166
|
||||
.reserve platform_PCIE_SBUS_LOCK_HOLD 0x166
|
||||
|
||||
.reserve platform_PEP0_PCIE_CLK_CTRL 0x15b
|
||||
.reserve platform_PEP1_PCIE_CLK_CTRL 0x15c
|
||||
.reserve platform_PEP2_PCIE_CLK_CTRL 0x15d
|
||||
.reserve platform_PEP3_PCIE_CLK_CTRL 0x15e
|
||||
.reserve platform_PEP4_PCIE_CLK_CTRL 0x15f
|
||||
.reserve platform_PEP5_PCIE_CLK_CTRL 0x160
|
||||
.reserve platform_PEP6_PCIE_CLK_CTRL 0x161
|
||||
.reserve platform_PEP7_PCIE_CLK_CTRL 0x162
|
||||
|
||||
.constant rrcc_SPI_TRANSFER_MODE, bootCfg_spiTransferMode
|
||||
.constant rrcc_SPI_TRANSFER_SPEED, bootCfg_spiTransferSpeed
|
||||
.constant rrcc_IMAGE_VERSION, platform_firmware_versionNumber
|
||||
|
||||
config_load_bootCfg_customMac:
|
||||
LOAD api_CUSTOM_MAC_BASE, bootCfg_customMac0, bootCfg_customMac1, bootCfg_customMac2, bootCfg_customMac3
|
||||
|
|
|
|||
Loading…
Reference in a new issue