WIP: Firmware platform, updated rrcc version

2021-01-02 15:46:37 +01:00 · 2021-01-02 15:46:37 +01:00 · 3d64f2328e
parent c56536f3e9
commit 3d64f2328e
8 changed files with 264 additions and 2 deletions
--- a/7
+++ b/7
@ -6,7 +6,12 @@ src/rrc-as: rrcc/CMakeLists.txt
 	cd rrcc && cmake . && make -j $(nproc)

 firmware.bin: src/rrc-as src/entrypoint.asm
-	rrcc/rrc-as src/entrypoint.asm firmware.bin
+	rrcc/rrc-as \
+	config.asm src/platform.asm \
+	src/entrypoint.asm \
+	src/clocking.asm \
+	src/pcie.asm \
+	firmware.bin

 clean:
 	-rm -f firmware.bin
--- a/README.md
+++ b/README.md
@ -11,3 +11,4 @@ WARNING: **This is a Work In Progress project**. Do not use on any cards you don
 ### Compilation
 * `$ make`
 * The firmware will be output to `firmware.bin`
+* You might want to change settings on file `config.asm` to fit your needs.
--- a/config.asm
+++ b/config.asm
@ -0,0 +1,21 @@
+; File used to declare configuration to be placed on the firmware image
+
+.constant firmware_versionNumber 0x0222 ; Define version reported back on register. 0x0222 = same as rrcBig_02.22
+
+; Picks between DEVICE_CFG.SystimeClockSource values. 0 = PCIE_REFCLK, 1 = IEEE1588_REFCLK
+.constant bootCfg_systimeClockSource 0
+
+.constant bootCfg_skipMemRepair 0
+.constant bootCfg_skipPcieInitialization 0
+
+; Picks between 0 = 8x8x, 1 = 4x4x4x4x
+.constant bootCfg_pep0_mode 0
+.constant bootCfg_pep2_mode 0
+.constant bootCfg_pep4_mode 0
+.constant bootCfg_pep6_mode 0
+
+; Custom macs are composed of two 32-bit values, reversed
+.constant bootCfg_customMac0 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
+.constant bootCfg_customMac1 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
+.constant bootCfg_customMac2 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
+.constant bootCfg_customMac3 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit bb6bcc8b5f42946d99be71963d17d393f4b300e8
+Subproject commit 8793c64f1cd9fbc9076c89190b6ef8b1c14f432d
--- a/src/clocking.asm
+++ b/src/clocking.asm
@ -0,0 +1,71 @@
+; Copyright (c) 2021, rrc-open-firmware FM10K-Documentation Contributors
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+;     * Redistributions of source code must retain the above copyright notice,
+;       this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of the copyright holder nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+init_startClocks:
+    MOV PLL_PCIE_CTRL,      0xfc640a        ; Nreset = 0, Enable = 1, Halt = 0, RefDiv = 1, FbDiv4 = 0, FbDiv255 = 0x19, OutDiv = 63, OutMuxSel = 0 (PCIE_REFCLK)
+    MOV PLL_EPL_CTRL,       0xfcb81a        ; Nreset = 0, Enable = 1, Halt = 0, RefDiv = 3, FbDiv4 = 0, FbDiv255 = 0x2E, OutDiv = 63, OutMuxSel = 0
+    MOV PLL_FABRIC_CTRL,    0x1cbc1a        ; Nreset = 0, Enable = 1, Halt = 0, RefDiv = 3, FbDiv4 = 0, FbDiv255 = 0x2F, OutDiv = 7, OutMuxSel = 0
+
+    SET PLL_PCIE_STAT,      0x40,   0x40    ; Value & Mask, set MiscCtrl, "Fast Calibration Mode" = 0, "Asynchronous load signal for PLL output divider." = 1
+    SET PLL_PCIE_STAT,      0,      0x40    ; Value & Mask, set MiscCtrl all 0 (?)
+    SET PLL_EPL_STAT,       0x40,   0x40    ; Value & Mask, set MiscCtrl, "Fast Calibration Mode" = 0, "Asynchronous load signal for PLL output divider." = 1
+    SET PLL_EPL_STAT,       0,      0x40    ; Value & Mask, set MiscCtrl all 0 (?)
+
+    BEQ CHIP_VERSION,       platform_STEPPING_A0, 0x7f, @.skip_XPLL_init ; Lower stepping did not have some initialization steps
+        MOV PCIE_XPLL_CTRL,     0x250c81    ; RefDiv = 1, FbDiv4 = 0, FbDiv255 = 0x19, OutDiv = 0xA, MiscCtrl[0] = 1 "Fast Calibration Mode"
+        MOV PCIE_CLK_CTRL,      0xf0        ; Nreset[0-3] = 0, Enable[0-3] = 1, Halt[0-3] = 0
+    .skip_XPLL_init:
+    WAIT                    50
+
+
+    MOV PLL_PCIE_CTRL,      0xfc640b        ; same as initial config
+    MOV PLL_EPL_CTRL,       0xfcb81b        ; same as initial config
+    MOV PLL_FABRIC_CTRL,    0x1cbc1b        ; same as initial config
+
+    BEQ CHIP_VERSION,       platform_STEPPING_A0, 0x7f, @.skip_CLK_set
+        MOV PCIE_CLK_CTRL,      0xff        ; Bring it back out of halt? Nreset[0-3] = 0, Enable[0-3] = 1, Halt[0-3] = 1
+    .skip_CLK_set:
+    WAIT                    100000
+
+    MOV PLL_PCIE_CTRL,      0x01fc640b      ; Bring it back to normal operation. Nreset = 1, Enable = 1, Halt = 0, RefDiv = 1, FbDiv4 = 0, FbDiv255 = 0x19, OutDiv = 63, OutMuxSel = 1 (PLL_PCIE_CLK)
+    MOV PLL_EPL_CTRL,       0x01fcb81b      ; Bring it back to normal operation. Nreset = 1, Enable = 1, Halt = 0, RefDiv = 3, FbDiv4 = 0, FbDiv255 = 0x2E, OutDiv = 63, OutMuxSel = 1 (PLL_PCIE_CLK)
+    MOV PLL_FABRIC_CTRL,    0x011cbc1b      ; Bring it back to normal operation. Nreset = 1, Enable = 1, Halt = 0, RefDiv = 3, FbDiv4 = 0, FbDiv255 = 0x2F, OutDiv = 7, OutMuxSel = 1 (PLL_PCIE_CLK)
+
+    WAIT                    10
+    RET
+
+; FASTCALL void(bool useSystimeClockSource)
+init_setClockSource:
+    BEQ P0,                 0, 0x1, @.return        ; If clock source is defined as system = 0
+        SET DEVICE_CFG,     0x10000, 0x10000  ; set DEVICE_CFG.SystimeClockSource to IEEE1588_REFCLK (default PCIE_REFCLK)
+    .return:
+    RET
+
+init_markClockStable:
+    SET SOFT_RESET, 0, 0x1      ; Clear ColdReset to mark clocks are set and stable
+    MOV api_BSM_STATUS, 0x0a    ; Set status for switch manager to know
+    MOV api_DE_COLD_RESET_STATUS, api_BSM_STATUS
+    RET
--- a/src/entrypoint.asm
+++ b/src/entrypoint.asm
@ -25,4 +25,80 @@


 entrypoint:
+    CALL @init_startClocks
+    FASTCALL @init_setClockSource, bootCfg_systimeClockSource
+    FASTCALL @init_setPcieSplitMode, bootCfg_pep0_mode, bootCfg_pep2_mode, bootCfg_pep4_mode, bootCfg_pep6_mode
+    SET DEVICE_CFG, 0xff80, 0xff80                          ; Set PCIeEnable[0-8] to enabled
+    CALL @init_markClockStable
+    CALL @init_markSbusBooted
+    FASTCALL @init_memoryRepairConfig, bootCfg_skipMemRepair
+    CALL @init_bistStateCheck
+    MOV R0, bootCfg_skipPcieInitialization
+    BEQ R0, 1, 1, @.skipPcieInit
+        SET SOFT_RESET, 0, 0x6 ; Enable areas, EPLReset = 0, SwitchReset = 0
+        WAIT 10 ; Wait 100ns, minimum
+        ; TODO complete this
+
+
+
+
+
+
+
+
+    .skipPcieInit:
+    BEQ platform_PCIE_SBUS_LOCK_HOLD, 1, 0x1, @.noReleaseLock
+        CALL @lock_PCIE_SBUS_release
+    .noReleaseLock:
+    CALL @config_load_bootCfg_customMac
+    MOV api_EEPROM_IMAGE_VERSION, firmware_versionNumber    ; Sets the version on memory where a switch manager can read it
+    RET
+
+init_markSbusBooted:
+    MOV api_BSM_STATUS, 0x0000b
+    MOV SBUS_EPL_CFG, 0 ; Set SBUS_ControllerReset = 0 (Not in reset)
+    MOV SBUS_PCIE_CFG, 0 ; Set SBUS_ControllerReset = 0 (Not in reset)
+    MOV api_BSM_STATUS, 0x1000b
+    MOV api_SBUS_RESET_STATUS, api_BSM_STATUS
+    RET
+
+; FASTCALL void(bool skipMemRepair)
+init_memoryRepairConfig:
+    MOV api_BSM_STATUS, 0x00000c ; apparently api_MEMORY_REPAIR_STATUS is not set here
+    BEQ P0, 0, 0x1, @.noSkipRepair
+        MOV api_BSM_STATUS, 0x41000c
+        MOV api_MEMORY_REPAIR_STATUS, api_BSM_STATUS
+        RET
+    .noSkipRepair:
+    MOV REI_CTRL, 0x9; Set RAM EFUSE interface, Reset = 1, Mode = 0, Run = 0, AutoLoadEnable = 1
+    MOV REI_CTRL, 0x8; Take it out of reset. Set RAM EFUSE interface, Reset = 0, Mode = 0, Run = 0, AutoLoadEnable = 1
+    MOV api_BSM_STATUS, 0x01000c ; apparently api_MEMORY_REPAIR_STATUS is not set here
+    MOV R0, 0x3 ; Number of total tries
+    .checkMemTest:
+    SUB R0, R0, 1 ; Decrease total tries
+    PNE REI_STAT, 1, 0x3, 16000, 10, @.failMemCheck ; Check if ReiDonePass = 1, and ReiDoneFail = 0
+        MOV api_BSM_STATUS, 0x11000c ; Success!
+        MOV api_MEMORY_REPAIR_STATUS, api_BSM_STATUS
+        WAIT 10
+        RET
+    .failMemCheck:
+    BEQ REI_STAT, 0x2, 0x2, @.failMem ; Check if ReiDoneFail = 1, and ReiDonePass = 0
+        MOV api_BSM_STATUS, 0x31000c ; Retry
+        MOV api_MEMORY_REPAIR_STATUS, api_BSM_STATUS
+        BNE R0, 0, 0x3, @.checkMemTest ; Jump if total tries != 0
+    .failMem: ; Failed or took too many tries
+    MOV api_BSM_STATUS, 0x21000c
+    MOV api_MEMORY_REPAIR_STATUS, api_BSM_STATUS
+    END     ; Program Execution finishes after memory check failed
+
+
+init_bistStateCheck:
+    MOV api_BSM_STATUS, 0x000000d
+    WRITE BIST_CTRL_0, 0x00000000, 0x0000ffff ; 64-bit write, regular BIST, BistRun_PCIE[0-8] = 1, BistRun_EPL = 1, BistRun_FABRIC = 1, BistRun_TUNNEL = 1, BistRun_BSM = 1, BistRun_CRM = 1, BistRun_FIBM = 1, BistRun_SBM = 1
+    WRITE BIST_CTRL_0, 0x0000ffff, 0x0000ffff ; 64-bit write, BIST memory init, BistRun_PCIE[0-8] = 1, BistRun_EPL = 1, BistRun_FABRIC = 1, BistRun_TUNNEL = 1, BistRun_BSM = 1, BistRun_CRM = 1, BistRun_FIBM = 1, BistRun_SBM = 1
+    WAIT 80000
+    WRITE BIST_CTRL_0, 0x00000000, 0x0000ffff ; 64-bit write, regular BIST, BistRun_PCIE[0-8] = 1, BistRun_EPL = 1, BistRun_FABRIC = 1, BistRun_TUNNEL = 1, BistRun_BSM = 1, BistRun_CRM = 1, BistRun_FIBM = 1, BistRun_SBM = 1
+    WRITE BIST_CTRL_0, 0x00000000, 0x00000000 ; 64-bit write, regular BIST, set all BistRun_* = 0
+    MOV api_BSM_STATUS, 0x110000d
+    MOV api_MEMORY_INIT_STATUS, api_BSM_STATUS
    RET
--- a/src/pcie.asm
+++ b/src/pcie.asm
@ -0,0 +1,53 @@
+; Copyright (c) 2021, rrc-open-firmware FM10K-Documentation Contributors
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+;     * Redistributions of source code must retain the above copyright notice,
+;       this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of the copyright holder nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+; FASTCALL void(bool pep0, bool pep2, bool pep4, bool pep6)
+init_setPcieSplitMode:
+    SET DEVICE_CFG, 0, 0xf ; Reset PCIe modes PCIeMode[0..3]
+    BEQ P0, 0, 0x1, @.continue0  ; PEP0
+        SET DEVICE_CFG, 0x1, 0x1 ; Set PCIeMode[0] = 1 (4x4x4x4)
+    .continue0:
+
+    BEQ P1, 0, 0x1, @.continue2  ; PEP2
+        SET DEVICE_CFG, 0x2, 0x2 ; Set PCIeMode[1] = 1 (4x4x4x4)
+    .continue2:
+
+    POPP R0, 1
+    BEQ R0, 0, 0x1, @.continue4  ; PEP4
+        SET DEVICE_CFG, 0x4, 0x4 ; Set PCIeMode[2] = 1 (4x4x4x4)
+    .continue4:
+
+    POPP R0, 2
+    BEQ R0, 0, 0x1, @.continue6  ; PEP6
+        SET DEVICE_CFG, 0x8, 0x8 ; Set PCIeMode[3] = 1 (4x4x4x4)
+    .continue6:
+    RET 2 ; Clear leftover two values in stack
+
+lock_PCIE_SBUS_release:
+    BNE api_PCIE_SBUS_LOCK_STATE, 1, 0x3, @.return ; If we hold the lock
+        SET api_PCIE_SBUS_LOCK_STATE, 0, 0x3 ; Release lock
+    .return:
+    RET
--- a/src/platform.asm
+++ b/src/platform.asm
@ -0,0 +1,35 @@
+; Copyright (c) 2021, rrc-open-firmware FM10K-Documentation Contributors
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+;     * Redistributions of source code must retain the above copyright notice,
+;       this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of the copyright holder nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+.constant platform_STEPPING_A0 0 ; Old FM10K?. Unknown features
+.constant platform_STEPPING_B0 1 ; Existing FM10K
+
+; Change this?
+.constant platform_PCIE_SBUS_LOCK_HOLD BSM_SCRATCH_START +0x166
+
+
+config_load_bootCfg_customMac:
+    LOAD api_CUSTOM_MAC_BASE, bootCfg_customMac0, bootCfg_customMac1, bootCfg_customMac2, bootCfg_customMac3
+    RET