Bump rrcc to fix FASTCALL and RET, added init_setPciePEPEnabled

config.asm

@@ -8,6 +8,16 @@
 .constant bootCfg_skipMemRepair 0
 .constant bootCfg_skipPcieInitialization 0
 
+.constant bootCfg_pep0_enable 1
+.constant bootCfg_pep1_enable 0
+.constant bootCfg_pep2_enable 1
+.constant bootCfg_pep3_enable 0
+.constant bootCfg_pep4_enable 1
+.constant bootCfg_pep5_enable 0
+.constant bootCfg_pep6_enable 1
+.constant bootCfg_pep7_enable 0
+.constant bootCfg_pep8_enable 0
+
 ; Picks between 0 = 8x8x, 1 = 4x4x4x4x
 .constant bootCfg_pep0_mode 0
 .constant bootCfg_pep2_mode 0

rrcc

@@ -1 +1 @@
-Subproject commit d70d63ee244bf9b654533ab1d5f4d33b295c699e
+Subproject commit 624fad13191c3077511d53cab59e19c9ed1aeecc

src/entrypoint.asm

@@ -28,7 +28,7 @@ entrypoint:
     CALL @init_startClocks
     FASTCALL @init_setClockSource, bootCfg_systimeClockSource
     FASTCALL @init_setPcieSplitMode, bootCfg_pep0_mode, bootCfg_pep2_mode, bootCfg_pep4_mode, bootCfg_pep6_mode
-    SET DEVICE_CFG, 0xff80, 0xff80                          ; Set PCIeEnable[0-8] to enabled
+    SET DEVICE_CFG, 0xff80, 0xff80 ; Set PCIeEnable[0-8] to enabled
     CALL @init_markClockStable
     CALL @init_markSbusBooted
     FASTCALL @init_memoryRepairConfig, bootCfg_skipMemRepair
@@ -37,6 +37,7 @@ entrypoint:
     BEQ R0, 1, 1, @.skipPcieInit
         SET SOFT_RESET, 0, 0x6 ; Enable areas, EPLReset = 0, SwitchReset = 0
         WAIT 10 ; Wait 100ns, minimum
+        FASTCALL @init_setPciePEPEnabled, bootCfg_pep0_enable, bootCfg_pep1_enable, bootCfg_pep2_enable, bootCfg_pep3_enable, bootCfg_pep4_enable, bootCfg_pep5_enable, bootCfg_pep6_enable, bootCfg_pep7_enable, bootCfg_pep8_enable
         ; TODO complete this
 
 

src/pcie.asm

@@ -42,7 +42,47 @@ init_setPcieSplitMode:
     BEQ~3 P3, 0, 0x1, @.continue6  ; access POPP 2 PEP6
         SET DEVICE_CFG, 0x8, 0x8 ; Set PCIeMode[3] = 1 (4x4x4x4)
     .continue6:
-    RET 2 ; Clear leftover two values in stack
+    RET
+
+; FASTCALL void(bool pep0, bool pep1, bool pep2, bool pep3, bool pep4, bool pep5, bool pep6, bool pep7, bool pep8)
+init_setPciePEPEnabled:
+    BEQ P0, 1, 0x1, @.continue0    ; PEP0
+         SET DEVICE_CFG, 0, 0x0080 ; Set PCIEnable[0] = 0, default 1
+    .continue0:
+
+    BEQ P1, 1, 0x1, @.continue1    ; PEP1
+         SET DEVICE_CFG, 0, 0x0100 ; Set PCIEnable[1] = 0, default 1
+    .continue1:
+
+    BEQ~3 P2, 1, 0x1, @.continue2    ; PEP2
+         SET DEVICE_CFG, 0, 0x0200 ; Set PCIEnable[2] = 0, default 1
+    .continue2:
+
+    BEQ~3 P3, 1, 0x1, @.continue3    ; PEP3
+         SET DEVICE_CFG, 0, 0x0400 ; Set PCIEnable[3] = 0, default 1
+    .continue3:
+
+    BEQ~3 P4, 1, 0x1, @.continue4    ; PEP4
+         SET DEVICE_CFG, 0, 0x0800 ; Set PCIEnable[4] = 0, default 1
+    .continue4:
+
+    BEQ~3 P5, 1, 0x1, @.continue5    ; PEP5
+         SET DEVICE_CFG, 0, 0x1000 ; Set PCIEnable[5] = 0, default 1
+    .continue5:
+
+    BEQ~3 P6, 1, 0x1, @.continue6    ; PEP6
+         SET DEVICE_CFG, 0, 0x2000 ; Set PCIEnable[6] = 0, default 1
+    .continue6:
+
+    BEQ~3 P7, 1, 0x1, @.continue7    ; PEP7
+         SET DEVICE_CFG, 0, 0x4000 ; Set PCIEnable[7] = 0, default 1
+    .continue7:
+
+    BEQ~3 P8, 1, 0x1, @.continue8    ; PEP8
+         SET DEVICE_CFG, 0, 0x8000 ; Set PCIEnable[8] = 0, default 1
+    .continue8:
+
+    RET
 
 lock_PCIE_SBUS_release:
     BNE api_PCIE_SBUS_LOCK_STATE, 1, 0x3, @.return ; If we hold the lock