diff --git a/README.md b/README.md index f2ba511..304474e 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Experimental project for replacing factory firmware on FM10000 cards with custom WARNING: **This is a Work In Progress project**. Do not use on any cards you don't want to have to unbrick via manual SPI connection. ### Requirements -* [rrcc](https://git.gammaspectra.live/FM10K/rrcc) (will build it from submodule) +* [rrcc](https://git.gammaspectra.live/FM10K/rrcc) (will be built from submodule, tagged to specific version. Make sure to do `$ git submodule update --init --recursive` before building) * make ### Compilation diff --git a/config.asm b/config.asm index bc82d3c..31ac550 100644 --- a/config.asm +++ b/config.asm @@ -1,10 +1,16 @@ ; File used to declare configuration to be placed on the firmware image +; Defaults to values found on Silicom PE3100G2DQiRM-QX4 card, as an example .constant platform_firmware_versionNumber 0x0222 ; Define version reported back on register. 0x0222 = same as rrcBig_02.22 +.constant bootCfg_spiTransferMode 0 +.constant bootCfg_spiTransferSpeed 7 + ; Picks between DEVICE_CFG.SystimeClockSource values. 0 = PCIE_REFCLK, 1 = IEEE1588_REFCLK .constant bootCfg_systimeClockSource 0 +.constant bootCfg_enableSwitchRdySignal 0 + .constant bootCfg_skipMemRepair 0 .constant bootCfg_skipPcieInitialization 0 @@ -24,6 +30,88 @@ .constant bootCfg_pep4_mode 0 .constant bootCfg_pep6_mode 0 +.constant bootCfg_pep0_numberOfLanes 8 +.constant bootCfg_pep1_numberOfLanes 0 +.constant bootCfg_pep2_numberOfLanes 8 +.constant bootCfg_pep3_numberOfLanes 0 +.constant bootCfg_pep4_numberOfLanes 8 +.constant bootCfg_pep5_numberOfLanes 0 +.constant bootCfg_pep6_numberOfLanes 8 +.constant bootCfg_pep7_numberOfLanes 0 +.constant bootCfg_pep8_numberOfLanes 0 + +.constant bootCfg_pep0_gen 3 +.constant bootCfg_pep1_gen 3 +.constant bootCfg_pep2_gen 3 +.constant bootCfg_pep3_gen 3 +.constant bootCfg_pep4_gen 3 +.constant bootCfg_pep5_gen 3 +.constant bootCfg_pep6_gen 3 +.constant bootCfg_pep7_gen 3 +.constant bootCfg_pep8_gen 3 + +.constant bootCfg_pep0_bar4Allowed 1 +.constant bootCfg_pep1_bar4Allowed 0 +.constant bootCfg_pep2_bar4Allowed 1 +.constant bootCfg_pep3_bar4Allowed 0 +.constant bootCfg_pep4_bar4Allowed 1 +.constant bootCfg_pep5_bar4Allowed 0 +.constant bootCfg_pep6_bar4Allowed 1 +.constant bootCfg_pep7_bar4Allowed 0 +.constant bootCfg_pep8_bar4Allowed 0 + +.constant bootCfg_pep0_ASPMEnable 0 +.constant bootCfg_pep1_ASPMEnable 0 +.constant bootCfg_pep2_ASPMEnable 0 +.constant bootCfg_pep3_ASPMEnable 0 +.constant bootCfg_pep4_ASPMEnable 0 +.constant bootCfg_pep5_ASPMEnable 0 +.constant bootCfg_pep6_ASPMEnable 0 +.constant bootCfg_pep7_ASPMEnable 0 +.constant bootCfg_pep8_ASPMEnable 0 + +.constant bootCfg_pep0_vendorId 0x8086 ; Intel Corporation +.constant bootCfg_pep1_vendorId 0x8086 +.constant bootCfg_pep2_vendorId 0x8086 +.constant bootCfg_pep3_vendorId 0x8086 +.constant bootCfg_pep4_vendorId 0x8086 +.constant bootCfg_pep5_vendorId 0x8086 +.constant bootCfg_pep6_vendorId 0x8086 +.constant bootCfg_pep7_vendorId 0x8086 +.constant bootCfg_pep8_vendorId 0x8086 + +.constant bootCfg_pep0_deviceId 0x15A4 ; Ethernet Switch FM10000 Host Interface +.constant bootCfg_pep1_deviceId 0x15A4 +.constant bootCfg_pep2_deviceId 0x15A4 +.constant bootCfg_pep3_deviceId 0x15A4 +.constant bootCfg_pep4_deviceId 0x15A4 +.constant bootCfg_pep5_deviceId 0x15A4 +.constant bootCfg_pep6_deviceId 0x15A4 +.constant bootCfg_pep7_deviceId 0x15A4 +.constant bootCfg_pep8_deviceId 0x15A4 + + +.constant bootCfg_pep0_subVendorId 0x1374 +.constant bootCfg_pep1_subVendorId 0x1374 +.constant bootCfg_pep2_subVendorId 0x1374 +.constant bootCfg_pep3_subVendorId 0x1374 +.constant bootCfg_pep4_subVendorId 0x1374 +.constant bootCfg_pep5_subVendorId 0x1374 +.constant bootCfg_pep6_subVendorId 0x1374 +.constant bootCfg_pep7_subVendorId 0x1374 +.constant bootCfg_pep8_subVendorId 0x1374 + +.constant bootCfg_pep0_subDeviceId 0x01C2 +.constant bootCfg_pep1_subDeviceId 0 +.constant bootCfg_pep2_subDeviceId 0x01C2 +.constant bootCfg_pep3_subDeviceId 0 +.constant bootCfg_pep4_subDeviceId 0x01C2 +.constant bootCfg_pep5_subDeviceId 0 +.constant bootCfg_pep6_subDeviceId 0x01C2 +.constant bootCfg_pep7_subDeviceId 0 +.constant bootCfg_pep8_subDeviceId 0 + + ; Custom macs are composed of two 32-bit values, reversed .constant bootCfg_customMac0 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00 .constant bootCfg_customMac1 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00 diff --git a/rrcc b/rrcc index 1566c33..e76befa 160000 --- a/rrcc +++ b/rrcc @@ -1 +1 @@ -Subproject commit 1566c33d5840c88df5ccb591849cda8965ddf628 +Subproject commit e76befaed778735115a0faa1559511368ba7b350 diff --git a/src/entrypoint.asm b/src/entrypoint.asm index 7d259fd..1516d1e 100644 --- a/src/entrypoint.asm +++ b/src/entrypoint.asm @@ -23,6 +23,9 @@ ; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.constant rrcc_SPI_TRANSFER_MODE, bootCfg_spiTransferMode +.constant rrcc_SPI_TRANSFER_SPEED, bootCfg_spiTransferSpeed +.constant rrcc_IMAGE_VERSION, platform_firmware_versionNumber entrypoint: CALL @init_startClocks