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Added PEP host interrupt handling (WIP)
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DataHoarder 2021-08-06 01:36:53 +02:00
parent fe66152b36
commit fe5e6906bc
5 changed files with 306 additions and 31 deletions
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2
rrcc

@ -1 +1 @@
Subproject commit 93a5ae1c1348e535ec038bd7de1316cd1f1618cf
Subproject commit 5d9ed3cd828c4aeace9dde35e86f3ed6ad644d5c

28
src/entrypoint.asm
View file

@ -86,72 +86,72 @@ entrypoint:
MOV R1, BSM_ADDR_OFFSET_1 ; Save any old offset
MOV BSM_ADDR_OFFSET_1, 0x000000 ; PCIe base address for PEP
MOV R0, 0x000007ff ; PCIE_IB settings, All enabled
SET R0, 0, PCIE_IB.VPD_Request ; Mask PCIE_IP.VPD_Request = 0
SET R0, 0, PCIE_IB.OutOfReset ; Mask PCIE_IP.OutOfReset = 0
SET R0, 0, PCIE_IB.DataPathReset ; Mask PCIE_IP.DataPathReset = 0
SET R0, 0, PCIE_IB.PFLR ; Mask PCIE_IP.PFLR = 0
MOV R0, 0x000007ff ; PCIE_IP settings, All enabled
SET R0, 0, PCIE_IP.VPD_Request ; Mask PCIE_IP.VPD_Request = 0
SET R0, 0, PCIE_IP.OutOfReset ; Mask PCIE_IP.OutOfReset = 0
SET R0, 0, PCIE_IP.DataPathReset ; Mask PCIE_IP.DataPathReset = 0
SET R0, 0, PCIE_IP.PFLR ; Mask PCIE_IP.PFLR = 0
; TODO: move this to pcie.asm and make it a function with looping
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_0, DEVICE_CFG.PCIeEnable_0, @.skip_PEP0_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_0, SOFT_RESET.PCIeActive_0 ; Set PEP0 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_0 ; Set PEP0 PCIeActive = 0
.skip_PEP0_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_1, DEVICE_CFG.PCIeEnable_1, @.skip_PEP1_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_1, SOFT_RESET.PCIeActive_1 ; Set PEP1 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_1 ; Set PEP1 PCIeActive = 0
.skip_PEP1_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_2, DEVICE_CFG.PCIeEnable_2, @.skip_PEP2_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_2, SOFT_RESET.PCIeActive_2 ; Set PEP2 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_2 ; Set PEP2 PCIeActive = 0
.skip_PEP2_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_3, DEVICE_CFG.PCIeEnable_3, @.skip_PEP3_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_3, SOFT_RESET.PCIeActive_3 ; Set PEP3 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_3 ; Set PEP3 PCIeActive = 0
.skip_PEP3_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_4, DEVICE_CFG.PCIeEnable_4, @.skip_PEP4_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_4, SOFT_RESET.PCIeActive_4 ; Set PEP4 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_4 ; Set PEP4 PCIeActive = 0
.skip_PEP4_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_5, DEVICE_CFG.PCIeEnable_5, @.skip_PEP5_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_5, SOFT_RESET.PCIeActive_5 ; Set PEP5 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_5 ; Set PEP5 PCIeActive = 0
.skip_PEP5_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_6, DEVICE_CFG.PCIeEnable_6, @.skip_PEP6_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_6, SOFT_RESET.PCIeActive_6 ; Set PEP6 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_6 ; Set PEP6 PCIeActive = 0
.skip_PEP6_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_7, DEVICE_CFG.PCIeEnable_7, @.skip_PEP7_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_7, SOFT_RESET.PCIeActive_7 ; Set PEP7 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_7 ; Set PEP7 PCIeActive = 0
.skip_PEP7_masking:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, tmp_PCIE_ADDRESS_OFFSET
BNE DEVICE_CFG, DEVICE_CFG.PCIeEnable_8, DEVICE_CFG.PCIeEnable_8, @.skip_PEP8_masking ; Is PCIeEnable != 1
SET SOFT_RESET SOFT_RESET.PCIeActive_8, SOFT_RESET.PCIeActive_8 ; Set PEP8 PCIeActive = 1
MOV~10 PCIE_IB, R0 ; Copy interrupt settings
MOV~10 PCIE_IP, R0 ; Copy interrupt settings
SET SOFT_RESET 0, SOFT_RESET.PCIeActive_8 ; Set PEP8 PCIeActive = 0
.skip_PEP8_masking:

232
src/interrupt.asm
View file

@ -29,6 +29,12 @@ interrupt_handler:
WRITE rrcc_STACK_POINTER, rrcc_STACK_START ; Reset Stack pointer to its starting position
;;WRITE R0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ; Zero R0 - RF
INIT R0, 16 ; Zero R0 - RF
MOV global_PEP_interrupts_counter, 0
INIT platform_PEP0_COUNTER, 9 ; Zero platform_PEP0_COUNTER - platform_PEP8_COUNTER
INIT platform_PEP0_COUNTER_2, 9 ; Zero platform_PEP0_COUNTER_2 - platform_PEP8_COUNTER_2
WRITE api_RE_RESET_MASK_STATUS_1, 0x00000000, 0x00000000 ; 64-bit write
.takeSoftResetLock: CALL @lock_soft_reset_take
@ -66,13 +72,224 @@ lock_soft_reset_release:
RET
interrupt_handle_each_source:
BNE GLOBAL_INTERRUPT_DETECT_0, INTERRUPTS_0.PCIE_BSM_0, INTERRUPTS_0.PCIE_BSM_0, @.skipPep0 ; Need to handle PEP 0
MOV api_BSM_STATUS, api_BSM_STATUS.Interrupt_Host_Y
CALL @interrupt_set_clocks_once_PEP0
.skipPep0:
; TODO complete this
MOV global_PEP_NUMBER, 0
.handleHostPEPsLoop:
MOV R1, 1
SHL R0, R1, global_PEP_NUMBER
AND R1, GLOBAL_INTERRUPT_DETECT_0, R0 ; Get specific INTERRUPTS_0.PCIE_BSM[0-8] field
BEQ R1, 0, 0xFFFFFFFF, @.skipPEP ; Skip if PEP number does not need handling
SHL R1, R0, 16 ; Set proper flags on status
OR R1, api_BSM_STATUS, api_BSM_STATUS.Interrupt_Host
MOV api_BSM_STATUS, R1
MOV R1, platform_PEP0_COUNTER &
ADD global_PEP_SCRATCH_ADDR, R1, global_PEP_NUMBER ; Set global_PEP_SCRATCH_ADDR according to current PEP
FASTCALL @interrupt_set_clocks_once_for_PEP, global_PEP_NUMBER
MOV BSM_ADDR_OFFSET_1, global_PEP_SCRATCH_ADDR
BNE~1 std_THIS, 0, 0xFFFFFFFF, @.donePEP ; If interrupt not handled, handle it (?)
.setupPEP:
FASTCALL @std_multiply, PCIE_PF_OFFSET, global_PEP_NUMBER
MOV BSM_ADDR_OFFSET_1, RRET ; pepNumber * PCIE_PF_OFFSET
BNE~1 PCIE_IP, PCIE_IP.OutOfReset, PCIE_IP.OutOfReset, @.skipPEPHandling ; If PCIE_IP not OutOfReset
SET api_BSM_STATUS, 0x01000000, 0x01000000 ; Interrupt Processing, OutOfReset
BEQ~1 PCIE_IP, PCIE_IP.PFLR, PCIE_IP.PFLR, @.skipPEPHandling ; If PCIE_IP has PFLR
BEQ~1 PCIE_IP, PCIE_IP.DataPathReset, PCIE_IP.DataPathReset, @.skipPEPHandling ; If PCIE_IP has DataPathReset
.handlePEP:
MOV BSM_ADDR_OFFSET_1, global_PEP_SCRATCH_ADDR
MOV~10 std_THIS, 0x01 ; Set PEP scratch status 0x1
MOV~01 global_PEP_interrupts_counter, std_THIS +9
ADD global_PEP_interrupts_counter, global_PEP_interrupts_counter, 1
FASTCALL @interrupt_handle_PEP, global_PEP_NUMBER
MOV BSM_ADDR_OFFSET_1, global_PEP_SCRATCH_ADDR
MOV~10 std_THIS, 0x02 ; Set PEP scratch status 0x2
MOV R1, 1
SHL R1, R1, global_PEP_NUMBER
OR api_RE_RESET_MASK_STATUS_1, api_RE_RESET_MASK_STATUS_1, R1
.skipPEPHandling:
MOV BSM_ADDR_OFFSET_1, global_PEP_SCRATCH_ADDR
MOV~10 std_THIS, 0x10 ; Set PEP scratch status 0x10
MOV BSM_ADDR_OFFSET_1, global_PEP_NUMBER
.donePEP: MOV~10 api_PCIE_ISR_STATUS_0, api_BSM_STATUS ; Set proper ISR status field based on offset
.skipPEP:
ADD global_PEP_NUMBER, global_PEP_NUMBER, 1
BNE global_PEP_NUMBER, 9, 0xFFFFFFFF, @.handleHostPEPsLoop ; Until PEP != 9 ( < 9, 0...8)
BEQ api_RE_RESET_MASK_STATUS_1, 0, 0x000001ff, @.ret ; No additional masks to handle reset, skip loop
WAIT 220000
MOV global_PEP_NUMBER, 0
.handleHostResetMaskLoop:
MOV R1, 1
SHL R0, R1, global_PEP_NUMBER
AND R1, api_RE_RESET_MASK_STATUS_1, R0 ; Get specific api_RE_RESET_MASK_STATUS_1 field
BEQ R1, 0, 0xFFFFFFFF, @.skipHostReset ; Skip if PEP number does not need handling
ADD BSM_ADDR_OFFSET_1, global_PEP_NUMBER, platform_PEP0_COUNTER & ; Set BSM_ADDR_OFFSET_1 according to current PEP scratch
ADD~1 std_THIS, std_THIS, 1
BNE std_THIS, 6, 0xf, @.skipUnknown
MOV~01 R0, std_THIS +9 ; Use second counter which is +9 off
SUB unknown_PEP_counter, global_PEP_interrupts_counter, R0 ; Use platform_PEP0_COUNTER_2
BEQ unknown_PEP_counter, 0, 0xfffffffc, @.skipUnknown
ADD~1 std_THIS, std_THIS, 1
.skipUnknown:
BNE platform_PEP0_COUNTER, 6, 0xf, @.skipHostReset
SET api_RE_RESET_MASK_STATUS_1, 0, R1
.skipHostReset:
ADD global_PEP_NUMBER, global_PEP_NUMBER, 1
BNE global_PEP_NUMBER, 9, 0xFFFFFFFF, @.handleHostResetMaskLoop ; Until PEP != 9 ( < 9, 0...8)
.ret: RET
; FASTCALL void(uint pepNumber)
interrupt_handle_PEP:
MOV R0, P0
FASTCALL @std_multiply, PCIE_PF_OFFSET, R0
MOV BSM_ADDR_OFFSET_1, RRET ; pepNumber * PCIE_PF_OFFSET
MOV~10 PCIE_IP, PCIE_IP.OutOfReset ; Clears OutOfReset bit on PCIE_IP (CW1)
FASTCALL @pcie_PEP_reset_enable, R0
FASTCALL @interrupt_PEP_SerDes_Interrupt, R0, 1
BEQ api_PCIE_SBUS_LOCK_STATE, platform_PCIE_SBUS_LOCK_NVM, 0x3, @.lockTaken ; Check if we have lock
.takeLock: CALL @lock_PCIE_SBUS_take
BNE RRET, 1, 0x1, @.takeLock ; We failed to take the lock
.lockTaken: FASTCALL @interrupt_handle_PEP_SerDes, R0
FASTCALL @pcie_PEP_reset_disable, R0
FASTCALL @interrupt_PEP_SerDes_Interrupt, R0, 0
RET
; FASTCALL void(uint pepNumber), uses R14 and R15
interrupt_handle_PEP_SerDes:
BNE P0, 8, 0xFFFFFFFF, @.notPEP8
MOV R14, 0x42
MOV R15, 0x43
JUMP @.exec
.notPEP8:
ADD R14, P0, 0xe0 ; PEP_DEV_0 = 0xe0 + pepNumber
ADD R15, P0, 0xd0 ; PEP_DEV_1 = 0xd0 + pepNumber
.exec:
FASTCALL @execute_SBus_PCIE_Command, 0x07, R14, 0, 0x00000011
BNE RRET, 1, 0x1, @.failCommand ; Command failed
WAIT 100
FASTCALL @execute_SBus_PCIE_Command, 0x07, R14, 0, 0x00000010
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x07, R14, 0, 0x00000002
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00060050
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00051032
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x0026000e
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00260102
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00260238
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00265202
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00265b01
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x002b0000
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00184240
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R14, 0, 0x00190084
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x03, R15, 0, 0x00022132
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x0f, R15, 0, 0x22041604
BNE RRET, 1, 0x1, @.failCommand ; Command failed
FASTCALL @execute_SBus_PCIE_Command, 0x12, R15, 0, 0x00009604
BNE RRET, 1, 0x1, @.failCommand ; Command failed
JUMP @.ret
.failCommand:
MOV api_SERDES_OOR_STATUS_PASS_1, 0x08000000 ; Write fail
OR api_SERDES_OOR_STATUS_PASS_1, api_SERDES_OOR_STATUS_PASS_1, R14
.ret: RET
; FASTCALL void(uint pepNumber, uint value), uses R14, R15
interrupt_PEP_SerDes_Interrupt:
MOV R14, P0
MOV R15, P1
FASTCALL @std_multiply, PCIE_PF_OFFSET, R14
MOV BSM_ADDR_OFFSET_1, RRET ; pepNumber * PCIE_PF_OFFSET
MOV~10 PCIE_SERDES_CTRL_0a, R15 ; PCIE_SERDES_CTRL_0a
MOV~10 PCIE_SERDES_CTRL_1a, R15 ; PCIE_SERDES_CTRL_1a
MOV~10 PCIE_SERDES_CTRL_2a, R15 ; PCIE_SERDES_CTRL_2a
MOV~10 PCIE_SERDES_CTRL_3a, R15 ; PCIE_SERDES_CTRL_3a
FASTCALL @pcie_get_PEP_mode R14
BEQ RRET, 0x1, 0x1, @.skip_pep_1x8 ; Skip if PEP Mode is 2x4
MOV~10 PCIE_SERDES_CTRL_4a, R15 ; PCIE_SERDES_CTRL_4a
MOV~10 PCIE_SERDES_CTRL_5a, R15 ; PCIE_SERDES_CTRL_5a
MOV~10 PCIE_SERDES_CTRL_6a, R15 ; PCIE_SERDES_CTRL_6a
MOV~10 PCIE_SERDES_CTRL_7a, R15 ; PCIE_SERDES_CTRL_7a
.skip_pep_1x8: RET
RET
; FASTCALL void(uint pepNumber)
; This could be made faster with custom RETURN. Better not to!
interrupt_set_clocks_once_for_PEP:
MOV R0, P0
BNE R0, 0, 0xFFFFFFFF, @.skipPEP0
CALL @interrupt_set_clocks_once_PEP0
JUMP @.ret
.skipPEP0:
BNE R0, 1, 0xFFFFFFFF, @.skipPEP1
CALL @interrupt_set_clocks_once_PEP1
JUMP @.ret
.skipPEP1:
BNE R0, 2, 0xFFFFFFFF, @.skipPEP2
CALL @interrupt_set_clocks_once_PEP2
JUMP @.ret
.skipPEP2:
BNE R0, 3, 0xFFFFFFFF, @.skipPEP3
CALL @interrupt_set_clocks_once_PEP3
JUMP @.ret
.skipPEP3:
BNE R0, 4, 0xFFFFFFFF, @.skipPEP4
CALL @interrupt_set_clocks_once_PEP4
JUMP @.ret
.skipPEP4:
BNE R0, 5, 0xFFFFFFFF, @.skipPEP5
CALL @interrupt_set_clocks_once_PEP5
JUMP @.ret
.skipPEP5:
BNE R0, 6, 0xFFFFFFFF, @.skipPEP6
CALL @interrupt_set_clocks_once_PEP6
JUMP @.ret
.skipPEP6:
BNE R0, 7, 0xFFFFFFFF, @.skipPEP7
CALL @interrupt_set_clocks_once_PEP7
JUMP @.ret
.skipPEP7:
BNE R0, 8, 0xFFFFFFFF, @.ret
CALL @interrupt_set_clocks_once_PEP8
.ret: RET
interrupt_set_clocks_once_PEP0:
BEQ CHIP_VERSION, 0x00, CHIP_VERSION.Version, @.skipReset
BEQ PCIE_CLK_CTRL, 0, PCIE_CLK_CTRL.Mode_0, @.skipReset ; If Mode for PEP group = PCIE_REFCLK
@ -159,4 +376,9 @@ interrupt_set_clocks_once_PEP7:
SET PCIE_CLK_CTRL, 0, PCIE_CLK_CTRL.Mode_6; Set Mode for PEP group = PCIE_REFCLK
SET SOFT_RESET, 0, SOFT_RESET.PCIeReset_7 ; Set PCIeReset for PEP = 0
.skipReset: SET SOFT_RESET, SOFT_RESET.PCIeActive_7, SOFT_RESET.PCIeActive_7 ; Set PCIeActive for PEP = 1
RET
interrupt_set_clocks_once_PEP8:
SET SOFT_RESET, SOFT_RESET.PCIeActive_8, SOFT_RESET.PCIeActive_8 ; Set PEP8 active via SOFT_RESET.PCIeActive_8
RET

47
src/pcie.asm
View file

@ -24,6 +24,31 @@
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; FASTCALL void(uint pepNumber) Uses R14 and R15. Alternatively could be implemented with branching
pcie_PEP_reset_enable:
ADD R14, P0, SOFT_RESET.PCIeReset.offset ; Create new shift offset
MOV R15, 1 ; Constant used on shift
SHL R14, R15, R14 ; R14 = 1 << (P0 + PCIeReset offset)
SET SOFT_RESET, R14, R14
RET
; FASTCALL void(uint pepNumber) Uses R14 and R15. Alternatively could be implemented with branching
pcie_PEP_reset_disable:
ADD R14, P0, SOFT_RESET.PCIeReset.offset ; Create new shift offset
MOV R15, 1 ; Constant used on shift
SHL R14, R15, R14 ; R14 = 1 << (P0 + PCIeReset offset)
SET SOFT_RESET, 0, R14
RET
; FASTCALL uint(uint pepNumber) Uses R15. Returns mode
pcie_get_PEP_mode:
SHR RRET, P0, 1 ; Divide pepNumber by 2
MOV R15, 1 ; Constant used on shift
SHL R15, R15, RRET ; R15 = 1 << (P0/2)
AND RRET, DEVICE_CFG, R15 ; Gets relevant PCIeMode field
SHR RRET, RRET, R15 ; RRET = result >> (P0/2)
RET ; RRET is already set
; FASTCALL void(bool pep0, bool pep2, bool pep4, bool pep6)
init_setPcieSplitMode:
SET DEVICE_CFG, 0, DEVICE_CFG.PCIeMode ; Reset PCIe modes PCIeMode[0..3]
@ -487,11 +512,11 @@ init_PCIE_SERDES_PCS:
MOV api_PCIE_PCS_EN_STATUS, api_BSM_STATUS
RET
; FASTCALL ??(bool P0, ____unused P1, PEP0, PEP1, PEP2, PEP3, PEP4, PEP5, PEP6, PEP7, PEP8)
; FASTCALL ??(bool P0 skipSettingReserved, ____unused P1, PEP0, PEP1, PEP2, PEP3, PEP4, PEP5, PEP6, PEP7, PEP8).. Uses R0, R1, R2
init_PCIE_SERDES_PCS_config:
MOV R0, 0, 0 ; Write R0 and R1
BEQ P0, 1, 0x1, @.skipSetting1toR0
MOV R0, 1
MOV R0, 1 ; Debug value? it hits Reserved field on PCIE_SERDES_CTRL
.skipSetting1toR0:
MOV R2, BSM_ADDR_OFFSET_1 ; Save offset 2
@ -559,7 +584,7 @@ init_PCIE_SERDES_PCS_config:
ADD BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_1, 0x100000
BEQ~2, P10, 0, 0x1, @.skip_PEP8_init ; Get PEP8 parameter
COPY~10, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_0a, R0, 2 ; Copy two words, only set first lanes as others are not accesible
.skip_PEP8_init:
SET api_BSM_STATUS, 0x10000000, 0x10000000
@ -567,14 +592,14 @@ init_PCIE_SERDES_PCS_config:
MOV BSM_ADDR_OFFSET_1, R2 ; Restore offset 1
RET
._init_PCIE_SERDES_PCS_config_doRegisterWrites_a:
COPY~10, PCIE_SERDES_CTRL_0, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_1, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_2, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_3, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_0a, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_1a, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_2a, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_3a, R0, 2 ; Copy two words
RET
._init_PCIE_SERDES_PCS_config_doRegisterWrites_b:
COPY~10, PCIE_SERDES_CTRL_4, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_5, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_6, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_7, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_4b, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_5b, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_6b, R0, 2 ; Copy two words
COPY~10, PCIE_SERDES_CTRL_7b, R0, 2 ; Copy two words
RET

28
src/platform.asm
View file

@ -57,6 +57,34 @@
.reserve platform_PEP6_PCIE_CLK_CTRL 0x161
.reserve platform_PEP7_PCIE_CLK_CTRL 0x162
.reserve global_PEP_NUMBER 0x154
.reserve unknown_PEP_counter 0x156
.reserve platform_PEP0_COUNTER 0x16b
.reserve platform_PEP1_COUNTER 0x16c
.reserve platform_PEP2_COUNTER 0x16d
.reserve platform_PEP3_COUNTER 0x16e
.reserve platform_PEP4_COUNTER 0x16f
.reserve platform_PEP5_COUNTER 0x170
.reserve platform_PEP6_COUNTER 0x171
.reserve platform_PEP7_COUNTER 0x172
.reserve platform_PEP8_COUNTER 0x173
.reserve platform_PEP0_COUNTER_2 0x174
.reserve platform_PEP1_COUNTER_2 0x175
.reserve platform_PEP2_COUNTER_2 0x176
.reserve platform_PEP3_COUNTER_2 0x177
.reserve platform_PEP4_COUNTER_2 0x178
.reserve platform_PEP5_COUNTER_2 0x179
.reserve platform_PEP6_COUNTER_2 0x17a
.reserve platform_PEP7_COUNTER_2 0x17b
.reserve platform_PEP8_COUNTER_2 0x17c
.reserve global_PEP_interrupts_counter 0x17d
.reserve global_PEP_SCRATCH_ADDR
.constant rrcc_SPI_TRANSFER_MODE, bootCfg_spiTransferMode
.constant rrcc_SPI_TRANSFER_SPEED, bootCfg_spiTransferSpeed
.constant rrcc_IMAGE_VERSION, platform_firmware_versionNumber