FM10K/rrcSmall
FM10K/rrcSmall
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Added more known registers defined in API
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This commit is contained in:
DataHoarder 2020-12-29 12:23:05 +01:00
parent d6aac8ce1d
commit aa6260ab91
2 changed files with 69 additions and 5 deletions
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4
src/OutputContext.cpp
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@ -65,7 +65,7 @@ std::string OutputContext::getDataHeader(uint32_t location) const {
std::string OutputContext::getDataEntry(uint32_t location, const std::string &representation) const {
std::string result = getDataHeader(location) + representation;
uint32_t padLength = 64;
uint32_t padLength = 80;
if (result.size() < padLength) {
result.append(padLength - result.size(), ' ');
}
@ -91,7 +91,7 @@ void OutputContext::analyze() {
bool justAbsolute = true;
bool justReturn = true;
for (auto &j : e.second) {
if (j.second != JumpKind::Return) {
if (j.second != JumpKind::Return && j.second != JumpKind::Speculative) {
justReturn = false;
}
if (j.second != JumpKind::Absolute && j.second != JumpKind::Speculative) {

70
src/main.cpp
View file

@ -123,14 +123,19 @@ void decodeImage(const std::string &fileName) {
{0x089380, "load_bootCfg_pep_ASPMEnable"},
{0x0839fc, "lock_PCIE_SBUS_take"},
{0x083aac, "lock_PCIE_SBUS_release"},
{0x083900, "execute_SerialBus_PCIE_Command"},
{0x080b00, "mark_SOFT_RESET_ClocksStable_ColdReset"},
{0x081100, "init_MASTER_SPICO"},
{0x0812ac, "FAIL_init_MASTER_SPICO"},
{0x08a004, "load_MASTER_SPICO_FW"},
{0x081400, "init_SERDES"},
{0x081b8c, "FAIL_init_SERDES"},
{0x08c004, "load_SERDES_FW"},
//Merge function
@ -148,12 +153,14 @@ void decodeImage(const std::string &fileName) {
{0x089160, "loc_089160_load_config_unknown_9"},
{0x089190, "loc_089190_load_config_unknown_9"},
{0x0891c0, "loc_0891c0_load_config_unknown_9"},
{0x089220, "loc_089220_load_config_unknown_1"},
{0x089220, "load_eeprom_major_version"},
{0x089290, "loc_089290_load_config_unknown_9"},
{0x0892c0, "loc_0892c0_load_config_unknown_9"},
{0x089320, "loc_089320_load_config_unknown_9"},
{0x089350, "loc_089350_load_config_unknown_9"},
{0x0893b0, "loc_0893b0_load_config_unknown_1"}
{0x0893b0, "load_bootCfg_skipPcieInitialization_skipMemRepair"},
{0x080d00, "config_memRepair"},
{0x0893c0, "load_pcie_clkmon_settings"},
};
knownNames[imageObject.getHeader().baseAddress] = "__ENTRYPOINT";
@ -177,6 +184,14 @@ void decodeImage(const std::string &fileName) {
{(uint32_t) KnownRegisters::MGMT_SCRATCH_0, "custom_RETURN_VALUE"},
{(uint32_t) KnownRegisters::MGMT_SCRATCH_1, "custom_RETURN_TO"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0, "api_SPI_LOCK_STATE"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 1, "api_PCIE_SBUS_LOCK_STATE"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 2, "api_SOFT_RESET_LOCK_STATE"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 3, "api_RECOVERY_STATUS_VECTOR"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 10, "api_PEP_MAC_BASE"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 100, "api_CUSTOM_MAC_BASE"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x141, "custom_PEP_CONFIG_serial0"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x142, "custom_PEP_CONFIG_serial1"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x143, "custom_PEP_CONFIG_mgmtPep"},
@ -198,6 +213,54 @@ void decodeImage(const std::string &fileName) {
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x132, "custom_param_RETURN_TO_SUCCESS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x133, "custom_param_RETURN_TO_FAILURE"},
/**
* api_BSM_STATUS: Step[0-7]
*
* Step 0x0D/0x0F: core = (bsmStatus >> 20 ) & 0xFFF;
* Step 0x0E: Master version ((bsmStatus >> 24) & 0x1), Master CRC ((bsmStatus >> 20) & 0x1), Serdes version ((bsmStatus >> 24) & 0x2), Serdes CRC ((bsmStatus >> 20) & 0x2)
* Step 0x11: host = (bsmStatus >> 16 ) & 0xF;
*/
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x190, "api_BSM_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x191, "api_EEPROM_IMAGE_VERSION"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x192, "api_MASTER_FW_VERSION"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x193, "api_SERDES_FW_VERSION"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x194, "api_SERDES_STATUS_1"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x195, "api_SERDES_STATUS_2"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x196, "api_SERDES_STATUS_3"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x197, "api_SERDES_STATUS_4"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x198, "api_PCIE_MASTER_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x199, "api_PCIE_SERDES_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1ae, "api_DE_COLD_RESET_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1af, "api_SBUS_RESET_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b0, "api_MEMORY_REPAIR_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b1, "api_MEMORY_INIT_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b2, "api_PCIE_PCS_DIS_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b3, "api_PCIE_MASTER_FW_DL_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b4, "api_PCIE_FW_CHECK_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b5, "api_PCIE_SERDES_FW_DL_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b6, "api_PCIE_SERDES_INIT_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b7, "api_PCIE_PCS_EN_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b8, "api_PCIE_DE_WARM_RESET_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1b9, "api_PCIE_ISR_STATUS_0"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1ba, "api_PCIE_ISR_STATUS_1"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1bb, "api_PCIE_ISR_STATUS_2"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1bc, "api_PCIE_ISR_STATUS_3"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1bd, "api_PCIE_ISR_STATUS_4"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1be, "api_PCIE_ISR_STATUS_5"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1bf, "api_PCIE_ISR_STATUS_6"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c0, "api_PCIE_ISR_STATUS_7"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c1, "api_PCIE_ISR_STATUS_8"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c2, "api_SERDES_OOR_STATUS_PASS_1"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c3, "api_SERDES_OOR_STATUS_PASS_2"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c4, "api_SW_LOCK_ERR_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c5, "api_PCIE_EN_REFCLK_STATUS"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c6, "api_RE_RESET_MASK_STATUS_1"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c7, "api_RE_RESET_MASK_STATUS_2"},
{(uint32_t) KnownRegisters::BSM_SCRATCH_START + 0x1c8, "api_RE_RESET_ERR_STATUS"},
};
for (auto &e : knownNames) {
@ -349,6 +412,7 @@ patchImage(const std::string &originalImage, const std::string &settingsFile, co
// 0x91c0 LOAD 9 ???? BSM_SCRATCH[0x13f] IF 0: JUMP 0x084da0 ELSE: PCIE_CTRL.RxLaneflipEn = 1
// ==0x91f0 LOAD 9 bar4Allowed + api.platform.config.switch.0.bootCfg.mgmtPep
// 0x9220 LOAD 1 = 0 EEPROM Major version (0x0222, 02.22 < first 0)
// ==0x9230 LOAD 9 vendor/device
// ==0x9260 LOAD 9 subVendor/subDevice
@ -359,7 +423,7 @@ patchImage(const std::string &originalImage, const std::string &settingsFile, co
// 0x9350 LOAD 9 ???? BSM_SCRATCH[0x17e], (val & 0x000000ff) something PCIe value?
// ==0x9380 LOAD 9 api.platform.config.switch.0.bootCfg.pep.0.ASPMEnable BSM_SCRATCH[0x17f] IF NOT 0: JUMP ELSE SET PCIE_CFG_PCIE_LINK_CAP.ActiveStateLinkPMSupport = 0
//
// 0x93b0 LOAD 1 = 0x00 ???? IF 0: JUMP 0x080d38 ELSE WRITE BSM_SCRATCH[0x1b0] = 0x41000c ???? DEAD code?
// 0x93b0 LOAD 1 = 0x00 api.platform.config.switch.0.bootCfg.skipMemRepair
// 0x93c0 LOAD 1 = 0x492550f0 PCIE_CLK_CTRL |= (value & 0xfffff0f0)
// 0x93cc LOAD 1 = 0x0000000f PCIE_CLK_CTRL_2 = value & 0xf
// 0x93d8 LOAD 1 = 0x00000064 PCIE_WARM_RESET_DELAY = value