Add further register bitfields

asm/registers.asm

@@ -5,7 +5,51 @@
 .constant LAST_FATAL_CODE, %0x1
 
 .constant SOFT_RESET, %0x3
+.bitfield SOFT_RESET.ColdReset 0
+.bitfield SOFT_RESET.EPLReset 1
+.bitfield SOFT_RESET.SwitchReset 2
+.bitfield SOFT_RESET.SwitchReady 3
+.bitfield SOFT_RESET.PCIeReset 4, 9
+.bitfield SOFT_RESET.PCIeReset_0 4
+.bitfield SOFT_RESET.PCIeReset_1 5
+.bitfield SOFT_RESET.PCIeReset_2 6
+.bitfield SOFT_RESET.PCIeReset_3 7
+.bitfield SOFT_RESET.PCIeReset_4 8
+.bitfield SOFT_RESET.PCIeReset_5 9
+.bitfield SOFT_RESET.PCIeReset_6 10
+.bitfield SOFT_RESET.PCIeReset_7 11
+.bitfield SOFT_RESET.PCIeReset_8 12
+.bitfield SOFT_RESET.PCIeActive 13, 9
+.bitfield SOFT_RESET.PCIeActive_0 13
+.bitfield SOFT_RESET.PCIeActive_1 14
+.bitfield SOFT_RESET.PCIeActive_2 15
+.bitfield SOFT_RESET.PCIeActive_3 16
+.bitfield SOFT_RESET.PCIeActive_4 17
+.bitfield SOFT_RESET.PCIeActive_5 18
+.bitfield SOFT_RESET.PCIeActive_6 19
+.bitfield SOFT_RESET.PCIeActive_7 20
+.bitfield SOFT_RESET.PCIeActive_8 21
+
 .constant DEVICE_CFG, %0x4
+.bitfield DEVICE_CFG.PCIeMode 0, 4
+.bitfield DEVICE_CFG.PCIeMode_0 0
+.bitfield DEVICE_CFG.PCIeMode_1 1
+.bitfield DEVICE_CFG.PCIeMode_2 2
+.bitfield DEVICE_CFG.PCIeMode_3 3
+.bitfield DEVICE_CFG.Eth100GDisabled 4
+.bitfield DEVICE_CFG.FeatureCode 5, 2
+.bitfield DEVICE_CFG.PCIeEnable 7, 9
+.bitfield DEVICE_CFG.PCIeEnable_0 7
+.bitfield DEVICE_CFG.PCIeEnable_1 8
+.bitfield DEVICE_CFG.PCIeEnable_2 9
+.bitfield DEVICE_CFG.PCIeEnable_3 10
+.bitfield DEVICE_CFG.PCIeEnable_4 11
+.bitfield DEVICE_CFG.PCIeEnable_5 12
+.bitfield DEVICE_CFG.PCIeEnable_6 13
+.bitfield DEVICE_CFG.PCIeEnable_7 14
+.bitfield DEVICE_CFG.PCIeEnable_8 15
+.bitfield DEVICE_CFG.SystimeClockSource 16
+
 .constant RESET_CFG, %0x5
 .constant WATCHDOG_CFG, %0x6
 
@@ -48,6 +92,7 @@
 .constant LSM_CLKOBS_CTRL, %0x450
 
 .constant CHIP_VERSION, %0x452
+.bitfield CHIP_VERSION.Version 0, 7
 
 .constant BSM_SCRATCH_START, %0x800
 .constant BSM_SCRATCH_END, BSM_SCRATCH_START +0x400
@@ -160,8 +205,42 @@
 .constant SYSTIME_CAPTURE_3_1, %0x225b
 
 .constant PCIE_XPLL_CTRL, %0x3000
+
 .constant PCIE_CLK_CTRL, %0x3001
+.bitfield PCIE_CLK_CTRL.Nreset 0, 4
+.bitfield PCIE_CLK_CTRL.Nreset_0 0
+.bitfield PCIE_CLK_CTRL.Nreset_1 1
+.bitfield PCIE_CLK_CTRL.Nreset_2 2
+.bitfield PCIE_CLK_CTRL.Nreset_3 3
+.bitfield PCIE_CLK_CTRL.Enable 4, 4
+.bitfield PCIE_CLK_CTRL.Enable_0 4
+.bitfield PCIE_CLK_CTRL.Enable_1 5
+.bitfield PCIE_CLK_CTRL.Enable_2 6
+.bitfield PCIE_CLK_CTRL.Enable_3 7
+.bitfield PCIE_CLK_CTRL.Halt 8, 4
+.bitfield PCIE_CLK_CTRL.Halt_0 8
+.bitfield PCIE_CLK_CTRL.Halt_1 9
+.bitfield PCIE_CLK_CTRL.Halt_2 10
+.bitfield PCIE_CLK_CTRL.Halt_3 11
+.bitfield PCIE_CLK_CTRL.OutMuxSel 12, 8
+.bitfield PCIE_CLK_CTRL.OutMuxSel_0 12, 2
+.bitfield PCIE_CLK_CTRL.OutMuxSel_0 14, 2
+.bitfield PCIE_CLK_CTRL.OutMuxSel_0 16, 2
+.bitfield PCIE_CLK_CTRL.OutMuxSel_0 18, 2
+.bitfield PCIE_CLK_CTRL.Mode 20, 12
+.bitfield PCIE_CLK_CTRL.Mode_0 20, 3
+.bitfield PCIE_CLK_CTRL.Mode_1 23, 3
+.bitfield PCIE_CLK_CTRL.Mode_2 26, 3
+.bitfield PCIE_CLK_CTRL.Mode_3 29, 3
+
 .constant PCIE_CLK_CTRL_2, %0x3002
+.bitfield PCIE_CLK_CTRL_2.XclkTerm 0, 4
+.bitfield PCIE_CLK_CTRL_2.XclkTerm_0 0
+.bitfield PCIE_CLK_CTRL_2.XclkTerm_1 1
+.bitfield PCIE_CLK_CTRL_2.XclkTerm_2 2
+.bitfield PCIE_CLK_CTRL_2.XclkTerm_3 3
+.bitfield PCIE_CLK_CTRL_2.ClkObs 4, 4
+
 .constant PCIE_CLKMON_RATIO_CFG, %0x3003
 .constant PCIE_CLKMON_TOLERANCE_CFG, %0x3004
 .constant PCIE_CLKMON_DEADLINES_CFG, %0x3005
@@ -172,7 +251,14 @@
 
 .constant PORTS_MGMT_BASE_ADDRESS, %0xE8000
 .constant PLL_EPL_CTRL, %0xE8000
+
 .constant PLL_EPL_STAT, %0xE8001
+.bitfield PLL_EPL_STAT.PllLocked 0
+.bitfield PLL_EPL_STAT.PllFreqChange 1
+.bitfield PLL_EPL_STAT.MiscCtrl.FastCalibrationMode 2
+.bitfield PLL_EPL_STAT.MiscCtrl.AsyncPLLLoadSignal 6
+.bitfield PLL_EPL_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2
+
 .constant PLL_FABRIC_CTRL, %0xE8002
 .constant PLL_FABRIC_STAT, %0xE8003
 .constant PLL_FABRIC_LOCK, %0xE8004