Fixed AsValue and AsIndirect

Fix PCIE_SERDES_CTRL registers
Added new ASM register fields, made std_divide use scratch registers
2021-08-06 00:14:58 +02:00 · 2021-08-06 00:06:15 +02:00 · 2021-08-06 00:04:44 +02:00 · 2021-08-05 16:29:29 +02:00 · 2021-08-05 16:01:18 +02:00
8 changed files with 83 additions and 39 deletions
--- a/.drone.jsonnet
+++ b/.drone.jsonnet
@ -35,8 +35,9 @@ local XbpsPipeline(image, version, arch, extra="") = Pipeline(image, version, ar
  AptPipeline("ubuntu", "20.04", "amd64", "g++"),
  AptPipeline("ubuntu", "20.04", "arm64", "g++"),

+  AptPipeline("debian", "bullseye", "amd64", "g++"),
+  AptPipeline("debian", "bullseye", "arm64", "g++"),
  AptPipeline("debian", "buster", "amd64", "g++"),
-  AptPipeline("debian", "buster", "arm64", "g++"),


  YumPipeline("fedora", "latest", "amd64", "g++"),
--- a/asm/api.asm
+++ b/asm/api.asm
@ -59,7 +59,18 @@
 .constant api_BSM_STATUS.PCIe_Warm_Reset_Deassert_Starting                      0x00000010 ;; PCIe warm reset deassert starting
 .constant api_BSM_STATUS.PCIe_Warm_Reset_Deassert_Completed                     0x00010010 ;; PCIe warm reset deassert completed
 .constant api_BSM_STATUS.ISR_Starting                                           0x000F0011 ;; ISR starting
-.constant api_BSM_STATUS.Interrupt_Host_Y                                       0x00000011 ;; Interrupt Host Y (mask 0xFFF0FFFF)
+
+.constant api_BSM_STATUS.Interrupt_Host                                         0x00000011 ;; Interrupt Host Y (mask 0xFFF0FFFF)
+.constant api_BSM_STATUS.Interrupt_Host_0                                       0x00000011
+.constant api_BSM_STATUS.Interrupt_Host_1                                       0x00010011
+.constant api_BSM_STATUS.Interrupt_Host_2                                       0x00020011
+.constant api_BSM_STATUS.Interrupt_Host_3                                       0x00030011
+.constant api_BSM_STATUS.Interrupt_Host_4                                       0x00040011
+.constant api_BSM_STATUS.Interrupt_Host_5                                       0x00050011
+.constant api_BSM_STATUS.Interrupt_Host_6                                       0x00060011
+.constant api_BSM_STATUS.Interrupt_Host_7                                       0x00070011
+.constant api_BSM_STATUS.Interrupt_Host_8                                       0x00080011
+
 .constant api_BSM_STATUS.Interrupt_Processing_OutOfReset                        0x01000011 ;; Interrupt Processing, OutOfReset (mask 0xFFF0FFFF)
 .constant api_BSM_STATUS.Interrupt_Processing_VPD                               0x02000011 ;; Interrupt Processing, VPD (mask 0xFFF0FFFF)
 .constant api_BSM_STATUS.Interrupt_Processing_HotReset                          0x04000011 ;; Interrupt Processing, HotReset (mask 0xFFF0FFFF)
--- a/asm/registers.asm
+++ b/asm/registers.asm
@ -358,27 +358,43 @@

 ;; These require offsets to be accessed
 .constant PCIE_PF_BASE, %0x100000
+.constant PCIE_PF_OFFSET, 0x100000

-.constant PCIE_IB, PCIE_PF_BASE +0x13000
-.bitfield PCIE_IB.HotReset 0
-.bitfield PCIE_IB.DeviceStateChange 1
-.bitfield PCIE_IB.Mailbox 2
-.bitfield PCIE_IB.VPD_Request 3
-.bitfield PCIE_IB.SramError 4
-.bitfield PCIE_IB.PFLR 5
-.bitfield PCIE_IB.DataPathReset 6
-.bitfield PCIE_IB.OutOfReset 7
-.bitfield PCIE_IB.NotInReset 8
-.bitfield PCIE_IB.Timeout 9
-.bitfield PCIE_IB.VFLR 10
+.constant PCIE_IP, PCIE_PF_BASE +0x13000
+.bitfield PCIE_IP.HotReset 0
+.bitfield PCIE_IP.DeviceStateChange 1
+.bitfield PCIE_IP.Mailbox 2
+.bitfield PCIE_IP.VPD_Request 3
+.bitfield PCIE_IP.SramError 4
+.bitfield PCIE_IP.PFLR 5
+.bitfield PCIE_IP.DataPathReset 6
+.bitfield PCIE_IP.OutOfReset 7
+.bitfield PCIE_IP.NotInReset 8
+.bitfield PCIE_IP.Timeout 9
+.bitfield PCIE_IP.VFLR 10

 .constant PCIE_IM, PCIE_PF_BASE +0x13001
 .constant PCIE_IB, PCIE_PF_BASE +0x13002
-.constant PCIE_SERDES_CTRL_0, PCIE_PF_BASE +0x19010
-.constant PCIE_SERDES_CTRL_1, PCIE_SERDES_CTRL_0 +2
-.constant PCIE_SERDES_CTRL_2, PCIE_SERDES_CTRL_1 +2
-.constant PCIE_SERDES_CTRL_3, PCIE_SERDES_CTRL_2 +2
-.constant PCIE_SERDES_CTRL_4, PCIE_SERDES_CTRL_3 +2
-.constant PCIE_SERDES_CTRL_5, PCIE_SERDES_CTRL_4 +2
-.constant PCIE_SERDES_CTRL_6, PCIE_SERDES_CTRL_5 +2
-.constant PCIE_SERDES_CTRL_7, PCIE_SERDES_CTRL_6 +2
+
+.bitfield PCIE_SERDES_CTRL_a.Interrupt 1
+.bitfield PCIE_SERDES_CTRL_a.InProgress 2
+.bitfield PCIE_SERDES_CTRL_a.InterruptCode 16, 16
+.bitfield PCIE_SERDES_CTRL_b.DataWrite 0, 16
+.bitfield PCIE_SERDES_CTRL_b.DataRead 16, 16
+
+.constant PCIE_SERDES_CTRL_0a, PCIE_PF_BASE +0x19010
+.constant PCIE_SERDES_CTRL_0b, PCIE_SERDES_CTRL_0a +1
+.constant PCIE_SERDES_CTRL_1a, PCIE_SERDES_CTRL_0a +2
+.constant PCIE_SERDES_CTRL_1b, PCIE_SERDES_CTRL_1a +1
+.constant PCIE_SERDES_CTRL_2a, PCIE_SERDES_CTRL_1a +2
+.constant PCIE_SERDES_CTRL_2b, PCIE_SERDES_CTRL_2a +1
+.constant PCIE_SERDES_CTRL_3a, PCIE_SERDES_CTRL_2a +2
+.constant PCIE_SERDES_CTRL_3b, PCIE_SERDES_CTRL_3a +1
+.constant PCIE_SERDES_CTRL_4a, PCIE_SERDES_CTRL_3a +2
+.constant PCIE_SERDES_CTRL_4b, PCIE_SERDES_CTRL_4a +1
+.constant PCIE_SERDES_CTRL_5a, PCIE_SERDES_CTRL_4a +2
+.constant PCIE_SERDES_CTRL_5b, PCIE_SERDES_CTRL_5a +1
+.constant PCIE_SERDES_CTRL_6a, PCIE_SERDES_CTRL_5a +2
+.constant PCIE_SERDES_CTRL_6b, PCIE_SERDES_CTRL_6a +1
+.constant PCIE_SERDES_CTRL_7a, PCIE_SERDES_CTRL_6a +2
+.constant PCIE_SERDES_CTRL_7b, PCIE_SERDES_CTRL_7a +1
--- a/asm/stdlib.asm
+++ b/asm/stdlib.asm
@ -10,6 +10,8 @@
 .reserve std_PARAMETER_0                  0x1E2
 .reserve std_PARAMETER_1                  0x1E3

+;; Used for offset pointer access
+.constant std_THIS                        %0

 .constant RRET                            std_RETURN_VALUE ;;Alias
 .constant RRET_X                          std_RETURN_VALUE_EXTRA ;;Alias
@ -55,7 +57,7 @@
 ;; Ephemeral registers to be used within functions. These values may not be kept when calling other functions. They can be used when returning values if necessary.
 ;; Some std functions might restore these values.
 .reserve std_EPHEMERAL_REGISTER_0         0x1F0
-.reserve std_EPHEMERAL_REGISTER_1        0x1F1
+.reserve std_EPHEMERAL_REGISTER_1         0x1F1
 .reserve std_EPHEMERAL_REGISTER_2         0x1F2
 .reserve std_EPHEMERAL_REGISTER_3         0x1F3
 .reserve std_EPHEMERAL_REGISTER_4         0x1F4
@ -123,16 +125,16 @@ std_divide:
    MOV BSM_COUNTER_0, 32           ; Move bits left to counter (8 * 4)
    MOV RRET, P0                    ; Move dividend to RRET (quotient)
    MOV RRET_X, 0                   ; Move remainder to RRET_X
-    MOV R0, 0
+    MOV S0, 0
    .divide:
-        MOV R0, RRET                ; Move quotient to temp R0
+        MOV S0, RRET                ; Move quotient to temp S0
        ADD RRET, RRET, RRET        ; quotient = quotient + quotient
        ADD RRET_X, RRET_X, RRET_X  ; remainder = remainder + remainder + ...
-        SHL R0, RRET, R0            ; quot << R0
-        ADD RRET_X, RRET_X, R0      ; remainder = ... + (quot << R0)
+        SHL S0, RRET, S0            ; quot << S0
+        ADD RRET_X, RRET_X, S0      ; remainder = ... + (quot << S0)

-        SUB R0, RRET_X, P1          ; compare rem >= divisor
-        BNE R0, 0, 1 <31, @.no_reduce
+        SUB S0, RRET_X, P1          ; compare rem >= divisor
+        BNE S0, 0, 1 <31, @.no_reduce
            SUB RRET_X, RRET_X, P1  ; remainder = remainder - divisor
            ADD RRET, RRET, 1       ; quotient = quotient + 1
        .no_reduce:
--- a/src/Parser.cpp
+++ b/src/Parser.cpp
@ -47,12 +47,12 @@ void Parser::parse() {
                    {{Token::Type::LocalLabel,   2}, {Token::Type::Operator,  3}, {Token::Type::Label,            1}, {Token::Type::Directive, 4}},

            /* 3 */
-                    {{Token::Type::Offset, 3}, {Token::Type::CodeLocation, 3}, {Token::Type::CodeLabel, 3}, {Token::Type::RegisterLocation, 3}, {Token::Type::Immediate, 3}, {Token::Type::BareValue, 3}},
+                    {{Token::Type::Offset, 3}, {Token::Type::CodeLocation, 3}, {Token::Type::CodeLabel, 3}, {Token::Type::RegisterLocation, 3}, {Token::Type::Immediate, 3}, {Token::Type::BareValue, 3}, {Token::Type::AsIndirect, 3}, {Token::Type::AsValue, 3}},

            /* 4 */
                    {{Token::Type::BareValue,    5}},
            /* 5 */
-                    {{Token::Type::Offset, 3}, {Token::Type::CodeLocation, 5}, {Token::Type::CodeLabel, 5}, {Token::Type::RegisterLocation, 5}, {Token::Type::Immediate, 5}, {Token::Type::BareValue, 5}},
+                    {{Token::Type::Offset, 3}, {Token::Type::CodeLocation, 5}, {Token::Type::CodeLabel, 5}, {Token::Type::RegisterLocation, 5}, {Token::Type::Immediate, 5}, {Token::Type::BareValue, 5}, {Token::Type::AsIndirect, 3}, {Token::Type::AsValue, 3}},

    };

--- a/src/instructions/Init.cpp
+++ b/src/instructions/Init.cpp
@ -58,6 +58,14 @@ std::vector<uint8_t> Instruction::Init::toBytes() const {
 std::unique_ptr<Instruction::Instruction>
 Instruction::Init::fromTokens(const Instruction::Instruction::parseOperatorResult &op,
                              const std::vector<Token> &tokens) {
-    //TODO
-    return nullptr;
+    return std::make_unique<Init>(
+            AddressWithOffset{tokens.at(0).getNumericValue(), op.offset1}, 1, tokens.at(1).getNumericValue(), tokens.size() > 2 ? tokens.at(2).getNumericValue() : 0, tokens.size() > 3 ? tokens.at(3).getNumericValue() : 0);
 }
+
+
+std::unique_ptr<Instruction::Instruction>
+Instruction::Init::fromDirectTokens(const Instruction::Instruction::parseOperatorResult &op,
+                              const std::vector<Token> &tokens) {
+    return std::make_unique<Init>(
+            AddressWithOffset{tokens.at(0).getNumericValue(), op.offset1}, 0, tokens.at(1).getNumericValue(), tokens.size() > 2 ? tokens.at(2).getNumericValue() : 0, tokens.size() > 3 ? tokens.at(3).getNumericValue() : 0);
+}
--- a/src/instructions/Init.h
+++ b/src/instructions/Init.h
@ -54,11 +54,14 @@ namespace Instruction {
        static std::unique_ptr<Instruction>
        fromTokens(const Instruction::parseOperatorResult &op, const std::vector<Token> &tokens);

+        static std::unique_ptr<Instruction>
+        fromDirectTokens(const Instruction::parseOperatorResult &op, const std::vector<Token> &tokens);

-        AddressWithOffset address;
-        uint8_t increment;
-        uint32_t count;
-        uint32_t data;
-        uint32_t data_add;
+
+        AddressWithOffset address{};
+        uint8_t increment{};
+        uint32_t count{};
+        uint32_t data{};
+        uint32_t data_add{};
    };
 }
--- a/src/instructions/Instruction.cpp
+++ b/src/instructions/Instruction.cpp
@ -82,11 +82,14 @@ namespace Instruction {
        addOperator("JUMP", 1, Jump::fromTokens);
        addOperator("RETURN", 1, Return::fromTokens);

-        //TODO INIT
        addOperator("WRITE", 2, Write::fromTokens);

        addOperator("COPY", 2, Copy::fromTokens);

+        // INIT <R> <count> [data] [data_add]
+        addOperator("INIT", 2, Init::fromTokens);
+        addOperator("INIT_DIRECT", 2, Init::fromDirectTokens);
+
        addOperator("LOAD", 2, Load::fromTokens);
        addOperator("LOAD_DIRECT", 2, Load::fromDirectTokens);
Author	SHA1	Message	Date
DataHoarder	5d9ed3cd82	Fixed AsValue and AsIndirect Some checks failed continuous-integration/drone Build is running Details continuous-integration/drone/push Build is failing Details	2021-08-06 00:14:58 +02:00
DataHoarder	c6d9b910df	Fix PCIE_SERDES_CTRL registers All checks were successful continuous-integration/drone/push Build is passing Details	2021-08-06 00:06:15 +02:00
DataHoarder	e3535abed0	Added new ASM register fields, made std_divide use scratch registers All checks were successful continuous-integration/drone/push Build is passing Details	2021-08-06 00:04:44 +02:00
DataHoarder	93a5ae1c13	Implemented INIT op All checks were successful continuous-integration/drone/push Build is passing Details	2021-08-05 16:29:29 +02:00
DataHoarder	30d8190bcb	Update CI to Debian bullseye	2021-08-05 16:01:18 +02:00