;; Definition of registers found on FM10000 ASIP ;; Based on Intel datasheet and BSD-3 code. .constant FATAL_CODE, %0x0 .constant LAST_FATAL_CODE, %0x1 .constant SOFT_RESET, %0x3 .bitfield SOFT_RESET.ColdReset 0 .bitfield SOFT_RESET.EPLReset 1 .bitfield SOFT_RESET.SwitchReset 2 .bitfield SOFT_RESET.SwitchReady 3 .bitfield SOFT_RESET.PCIeReset 4, 9 .bitfield SOFT_RESET.PCIeReset_0 4 .bitfield SOFT_RESET.PCIeReset_1 5 .bitfield SOFT_RESET.PCIeReset_2 6 .bitfield SOFT_RESET.PCIeReset_3 7 .bitfield SOFT_RESET.PCIeReset_4 8 .bitfield SOFT_RESET.PCIeReset_5 9 .bitfield SOFT_RESET.PCIeReset_6 10 .bitfield SOFT_RESET.PCIeReset_7 11 .bitfield SOFT_RESET.PCIeReset_8 12 .bitfield SOFT_RESET.PCIeActive 13, 9 .bitfield SOFT_RESET.PCIeActive_0 13 .bitfield SOFT_RESET.PCIeActive_1 14 .bitfield SOFT_RESET.PCIeActive_2 15 .bitfield SOFT_RESET.PCIeActive_3 16 .bitfield SOFT_RESET.PCIeActive_4 17 .bitfield SOFT_RESET.PCIeActive_5 18 .bitfield SOFT_RESET.PCIeActive_6 19 .bitfield SOFT_RESET.PCIeActive_7 20 .bitfield SOFT_RESET.PCIeActive_8 21 .constant DEVICE_CFG, %0x4 .bitfield DEVICE_CFG.PCIeMode 0, 4 .bitfield DEVICE_CFG.PCIeMode_0 0 .bitfield DEVICE_CFG.PCIeMode_2 1 .bitfield DEVICE_CFG.PCIeMode_4 2 .bitfield DEVICE_CFG.PCIeMode_6 3 .bitfield DEVICE_CFG.Eth100GDisabled 4 .bitfield DEVICE_CFG.FeatureCode 5, 2 .bitfield DEVICE_CFG.PCIeEnable 7, 9 .bitfield DEVICE_CFG.PCIeEnable_0 7 .bitfield DEVICE_CFG.PCIeEnable_1 8 .bitfield DEVICE_CFG.PCIeEnable_2 9 .bitfield DEVICE_CFG.PCIeEnable_3 10 .bitfield DEVICE_CFG.PCIeEnable_4 11 .bitfield DEVICE_CFG.PCIeEnable_5 12 .bitfield DEVICE_CFG.PCIeEnable_6 13 .bitfield DEVICE_CFG.PCIeEnable_7 14 .bitfield DEVICE_CFG.PCIeEnable_8 15 .bitfield DEVICE_CFG.SystimeClockSource 16 .constant RESET_CFG, %0x5 .constant WATCHDOG_CFG, %0x6 .constant MGMT_SCRATCH_0, %0x8 .constant MGMT_SCRATCH_1, MGMT_SCRATCH_0 +1 .constant VITAL_PRODUCT_DATA, %0x304 .bitfield VITAL_PRODUCT_DATA.PartNumber 0, 16 ;; These are the interrupts detect/mask that exist. All use same bitfields .constant GLOBAL_INTERRUPT_DETECT_0, %0x400 .constant GLOBAL_INTERRUPT_DETECT_1, %0x401 .constant INTERRUPT_MASK_INT_0, %0x402 .constant INTERRUPT_MASK_INT_1, %0x403 .constant INTERRUPT_MASK_PCIE_0, %0x420 .constant INTERRUPT_MASK_PCIE_1, %0x422 .constant INTERRUPT_MASK_PCIE_2, %0x424 .constant INTERRUPT_MASK_PCIE_3, %0x426 .constant INTERRUPT_MASK_PCIE_4, %0x428 .constant INTERRUPT_MASK_PCIE_5, %0x42a .constant INTERRUPT_MASK_PCIE_6, %0x42c .constant INTERRUPT_MASK_PCIE_7, %0x42e .constant INTERRUPT_MASK_PCIE_8, %0x431 .constant INTERRUPT_MASK_FIBM_0, %0x440 .constant INTERRUPT_MASK_FIBM_1, %0x441 .constant INTERRUPT_MASK_BSM_0, %0x442 .constant INTERRUPT_MASK_BSM_1, %0x443 .bitfield INTERRUPTS_0.PCIE_BSM 0, 9 .bitfield INTERRUPTS_0.PCIE_BSM_0 0 .bitfield INTERRUPTS_0.PCIE_BSM_1 1 .bitfield INTERRUPTS_0.PCIE_BSM_2 2 .bitfield INTERRUPTS_0.PCIE_BSM_3 3 .bitfield INTERRUPTS_0.PCIE_BSM_4 4 .bitfield INTERRUPTS_0.PCIE_BSM_5 5 .bitfield INTERRUPTS_0.PCIE_BSM_6 6 .bitfield INTERRUPTS_0.PCIE_BSM_7 7 .bitfield INTERRUPTS_0.PCIE_BSM_8 8 .bitfield INTERRUPTS_0.PCIE 9, 9 .bitfield INTERRUPTS_0.PCIE_0 9 .bitfield INTERRUPTS_0.PCIE_1 10 .bitfield INTERRUPTS_0.PCIE_2 11 .bitfield INTERRUPTS_0.PCIE_3 12 .bitfield INTERRUPTS_0.PCIE_4 13 .bitfield INTERRUPTS_0.PCIE_5 14 .bitfield INTERRUPTS_0.PCIE_6 15 .bitfield INTERRUPTS_0.PCIE_7 16 .bitfield INTERRUPTS_0.PCIE_8 17 .bitfield INTERRUPTS_0.EPL 18, 9 .bitfield INTERRUPTS_0.EPL_0 18 .bitfield INTERRUPTS_0.EPL_1 19 .bitfield INTERRUPTS_0.EPL_2 20 .bitfield INTERRUPTS_0.EPL_3 21 .bitfield INTERRUPTS_0.EPL_4 22 .bitfield INTERRUPTS_0.EPL_5 23 .bitfield INTERRUPTS_0.EPL_6 24 .bitfield INTERRUPTS_0.EPL_7 25 .bitfield INTERRUPTS_0.EPL_8 26 .bitfield INTERRUPTS_0.TUNNEL 27, 2 .bitfield INTERRUPTS_0.TUNNEL_0 27 .bitfield INTERRUPTS_0.TUNNEL_1 28 .bitfield INTERRUPTS_0.CORE, 29 .bitfield INTERRUPTS_0.SOFTWARE, 30 .bitfield INTERRUPTS_0.GPIO, 31 .bitfield INTERRUPTS_1.I2C, 0 .bitfield INTERRUPTS_1.MDIO, 1 .bitfield INTERRUPTS_1.CRM, 2 .bitfield INTERRUPTS_1.FH_TAIL, 3 .bitfield INTERRUPTS_1.FH_HEAD, 4 .bitfield INTERRUPTS_1.SBUS_EPL, 5 .bitfield INTERRUPTS_1.SBUS_PCIE, 6 .bitfield INTERRUPTS_1.PINS, 7 .bitfield INTERRUPTS_1.FIBM, 8 .bitfield INTERRUPTS_1.BSM, 9 .bitfield INTERRUPTS_1.XCLK, 10 .constant CORE_INTERRUPT_DETECT, %0x444 .constant CORE_INTERRUPT_MASK, %0x445 .constant SRAM_ERR_IP_0, %0x446 .constant SRAM_ERR_IP_1, %0x447 .constant SRAM_ERR_IM_0, %0x448 .constant SRAM_ERR_IM_1, %0x449 .constant PINS_STAT, %0x44a .constant PINS_IP, %0x44b .constant PINS_IM, %0x44c .constant SW_IP, %0x44d .constant SW_IM, %0x44e .constant SW_TEST_AND_SET, %0x44f .constant LSM_CLKOBS_CTRL, %0x450 .constant CHIP_VERSION, %0x452 .bitfield CHIP_VERSION.Version 0, 7 .constant BSM_SCRATCH_START, %0x800 .constant BSM_SCRATCH_END, BSM_SCRATCH_START +0x400 .constant BSM_CTRL, %0x000C00 .constant BSM_ARGS, %0x000C01 .constant BSM_ADDR_OFFSET_0, %0x000C04 .constant BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_0 +1 .constant BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_0 +2 .constant BSM_ADDR_OFFSET_3, BSM_ADDR_OFFSET_0 +3 .constant BSM_COUNTER_0, %0x000C08 .constant BSM_COUNTER_1, BSM_COUNTER_0 +1 .constant BSM_SRAM_CTRL, %0x000C0A .constant BSM_IP, %0x000C0B .constant BSM_IM, %0x000C0C .constant PIN_STRAP_STAT, %0x000C0D .constant FUSE_DATA_0, %0x000C0E .constant FUSE_DATA_1, %0x000C0F .constant BIST_CTRL_0, %0x000C10 .constant BIST_CTRL_1, %0x000C11 .constant REI_CTRL, %0x000C12 .constant REI_STAT, %0x000C13 .constant GPIO_CFG, %0x000C15 .constant GPIO_DATA, %0x000C16 .constant GPIO_IP, %0x000C17 .constant GPIO_IM, %0x000C18 .constant I2C_CFG, %0x000C19 .constant I2C_DATA_0, %0x000C1C .constant I2C_DATA_1, %0x000C1D .constant I2C_DATA_2, %0x000C1E .constant I2C_CTRL, %0x000C20 .constant MDIO_CFG, %0x000C22 .constant MDIO_DATA, %0x000C23 .constant MDIO_CTRL, %0x000C24 .constant SPI_TX_DATA, %0x000C26 .constant SPI_RX_DATA, %0x000C27 .constant SPI_HEADER, %0x000C28 .constant SPI_CTRL, %0x000C29 .constant LED_CFG, %0x000C2B .constant SCAN_DATA_IN, %0x000C2D .constant CRM_DATA_START, %0x001000 ;; 2048 entries, each one 2 words .constant CRM_DATA_END, %0x001FFF .constant CRM_CTRL, %0x002000 .constant CRM_STATUS, %0x002001 .constant CRM_TIME, %0x002002 .constant CRM_SRAM_CTRL, %0x002004 .constant CRM_IP, %0x002008 .constant CRM_IM, %0x00200C .constant CRM_COMMAND_START, %0x002080 ;; 64 entries, each one 2 words .constant CRM_COMMAND_END, %0x0020FF .constant CRM_REGISTER_START, %0x002100 ;; 64 entries, each one 2 words .constant CRM_REGISTER_END, %0x00217F .constant CRM_PERIOD_START, %0x002180 ;; 64 entries, each one 2 words .constant CRM_PERIOD_END, %0x0021FF .constant CRM_PARAM_START, %0x002200 ;; 64 entries, each one 1 words .constant CRM_PARAM_END, %0x002240 .constant PLL_PCIE_CTRL, %0x2241 .bitfield PLL_PCIE_CTRL.Nreset 0 .bitfield PLL_PCIE_CTRL.NEnable 1 .bitfield PLL_PCIE_CTRL.Halt 2 .bitfield PLL_PCIE_CTRL.RefDiv 3, 6 .bitfield PLL_PCIE_CTRL.FbDiv4 9 .bitfield PLL_PCIE_CTRL.FbDiv255 10, 8 .bitfield PLL_PCIE_CTRL.OutDiv 18, 6 .bitfield PLL_PCIE_CTRL.OutMuxSel 24, 3 .constant PLL_PCIE_STAT, %0x2242 .bitfield PLL_PCIE_STAT.PllLocked 0 .bitfield PLL_PCIE_STAT.PllFreqChange 1 .bitfield PLL_PCIE_STAT.MiscCtrl.FastCalibrationMode 2 .bitfield PLL_PCIE_STAT.MiscCtrl.AsyncPLLLoadSignal 6 .bitfield PLL_PCIE_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2 .constant SBUS_PCIE_CFG, %0x2243 .constant SBUS_PCIE_COMMAND, %0x2244 .bitfield SBUS_PCIE_COMMAND.Register 0, 8 .bitfield SBUS_PCIE_COMMAND.Address 8, 8 .bitfield SBUS_PCIE_COMMAND.Op 16, 8 .bitfield SBUS_PCIE_COMMAND.Execute 24 .bitfield SBUS_PCIE_COMMAND.Busy 25 .bitfield SBUS_PCIE_COMMAND.ResultCode 26, 3 .constant SBUS_PCIE_REQUEST, %0x2245 .constant SBUS_PCIE_RESPONSE, %0x2246 .constant SBUS_PCIE_SPICO_IN, %0x2247 .constant SBUS_PCIE_SPICO_OUT, %0x2248 .constant SBUS_PCIE_IP, %0x2249 .constant SBUS_PCIE_IM, %0x224a .constant SYSTIME_CFG_0, %0x224C .constant SYSTIME_CFG_1, %0x224D .constant SYSTIME_0, %0x224E .constant SYSTIME_1, %0x224F .constant SYSTIME0_0, %0x2250 .constant SYSTIME0_1, %0x2251 .constant SYSTIME_PULSE_0, %0x2252 .constant SYSTIME_PULSE_1, %0x2253 .constant SYSTIME_CAPTURE_0_0, %0x2254 .constant SYSTIME_CAPTURE_0_1, %0x2255 .constant SYSTIME_CAPTURE_1_0, %0x2256 .constant SYSTIME_CAPTURE_1_1, %0x2257 .constant SYSTIME_CAPTURE_2_0, %0x2258 .constant SYSTIME_CAPTURE_2_1, %0x2259 .constant SYSTIME_CAPTURE_3_0, %0x225a .constant SYSTIME_CAPTURE_3_1, %0x225b .constant PCIE_XPLL_CTRL, %0x3000 .constant PCIE_CLK_CTRL, %0x3001 .bitfield PCIE_CLK_CTRL.Nreset 0, 4 .bitfield PCIE_CLK_CTRL.Nreset_0 0 .bitfield PCIE_CLK_CTRL.Nreset_2 1 .bitfield PCIE_CLK_CTRL.Nreset_4 2 .bitfield PCIE_CLK_CTRL.Nreset_6 3 .bitfield PCIE_CLK_CTRL.Enable 4, 4 .bitfield PCIE_CLK_CTRL.Enable_0 4 .bitfield PCIE_CLK_CTRL.Enable_2 5 .bitfield PCIE_CLK_CTRL.Enable_4 6 .bitfield PCIE_CLK_CTRL.Enable_6 7 .bitfield PCIE_CLK_CTRL.Halt 8, 4 .bitfield PCIE_CLK_CTRL.Halt_0 8 .bitfield PCIE_CLK_CTRL.Halt_2 9 .bitfield PCIE_CLK_CTRL.Halt_4 10 .bitfield PCIE_CLK_CTRL.Halt_6 11 .bitfield PCIE_CLK_CTRL.OutMuxSel 12, 8 .bitfield PCIE_CLK_CTRL.OutMuxSel_0 12, 2 .bitfield PCIE_CLK_CTRL.OutMuxSel_2 14, 2 .bitfield PCIE_CLK_CTRL.OutMuxSel_4 16, 2 .bitfield PCIE_CLK_CTRL.OutMuxSel_6 18, 2 .bitfield PCIE_CLK_CTRL.Mode 20, 12 .bitfield PCIE_CLK_CTRL.Mode_0 20, 3 .bitfield PCIE_CLK_CTRL.Mode_2 23, 3 .bitfield PCIE_CLK_CTRL.Mode_4 26, 3 .bitfield PCIE_CLK_CTRL.Mode_6 29, 3 .constant PCIE_CLK_CTRL_2, %0x3002 .bitfield PCIE_CLK_CTRL_2.XclkTerm 0, 4 .bitfield PCIE_CLK_CTRL_2.XclkTerm_0 0 .bitfield PCIE_CLK_CTRL_2.XclkTerm_2 1 .bitfield PCIE_CLK_CTRL_2.XclkTerm_4 2 .bitfield PCIE_CLK_CTRL_2.XclkTerm_6 3 .bitfield PCIE_CLK_CTRL_2.ClkObs 4, 4 .constant PCIE_CLKMON_RATIO_CFG, %0x3003 .constant PCIE_CLKMON_TOLERANCE_CFG, %0x3004 .constant PCIE_CLKMON_DEADLINES_CFG, %0x3005 .constant PCIE_CLK_STAT, %0x3006 .bitfield PCIE_CLK_STAT.PllLocked 0, 4 .bitfield PCIE_CLK_STAT.PllLocked_0 0 .bitfield PCIE_CLK_STAT.PllLocked_2 1 .bitfield PCIE_CLK_STAT.PllLocked_4 2 .bitfield PCIE_CLK_STAT.PllLocked_6 3 .bitfield PCIE_CLK_STAT.PllFreqChange 4, 4 .bitfield PCIE_CLK_STAT.PllFreqChange_0 4 .bitfield PCIE_CLK_STAT.PllFreqChange_2 5 .bitfield PCIE_CLK_STAT.PllFreqChange_4 6 .bitfield PCIE_CLK_STAT.PllFreqChange_6 7 .bitfield PCIE_CLK_STAT.RefclkSel 8, 4 .bitfield PCIE_CLK_STAT.RefclkSel_0 8 .bitfield PCIE_CLK_STAT.RefclkSel_2 9 .bitfield PCIE_CLK_STAT.RefclkSel_4 10 .bitfield PCIE_CLK_STAT.RefclkSel_6 11 .bitfield PCIE_CLK_STAT.XRefclkValid 12, 4 .bitfield PCIE_CLK_STAT.XRefclkValid_0 12 .bitfield PCIE_CLK_STAT.XRefclkValid_2 13 .bitfield PCIE_CLK_STAT.XRefclkValid_4 14 .bitfield PCIE_CLK_STAT.XRefclkValid_6 15 .constant PCIE_CLK_IP, %0x3007 .constant PCIE_CLK_IM, %0x3008 .constant PCIE_WARM_RESET_DELAY, %0x3009 .constant PORTS_MGMT_BASE_ADDRESS, %0xE8000 .constant PLL_EPL_CTRL, %0xE8000 .constant PLL_EPL_STAT, %0xE8001 .bitfield PLL_EPL_STAT.PllLocked 0 .bitfield PLL_EPL_STAT.PllFreqChange 1 .bitfield PLL_EPL_STAT.MiscCtrl.FastCalibrationMode 2 .bitfield PLL_EPL_STAT.MiscCtrl.AsyncPLLLoadSignal 6 .bitfield PLL_EPL_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2 .constant PLL_FABRIC_CTRL, %0xE8002 .constant PLL_FABRIC_STAT, %0xE8003 .constant PLL_FABRIC_LOCK, %0xE8004 .constant SBUS_EPL_CFG, %0xE8005 .constant SBUS_EPL_COMMAND, %0xE8006 .constant SBUS_EPL_REQUEST, %0xE8007 .constant SBUS_EPL_RESPONSE, %0xE8008 .constant SBUS_EPL_SPICO_IN, %0xE8009 .constant SBUS_EPL_SPICO_OUT, %0xE800a .constant SBUS_EPL_IP, %0xE800b .constant SBUS_EPL_IM, %0xE800c .constant PM_CLKOBS_CTRL, %0xE8012 ;; These require offsets to be accessed .constant PCIE_PF_BASE, %0x100000 .constant PCIE_PF_OFFSET, 0x100000 .constant PCIE_IP, PCIE_PF_BASE +0x13000 .bitfield PCIE_IP.HotReset 0 .bitfield PCIE_IP.DeviceStateChange 1 .bitfield PCIE_IP.Mailbox 2 .bitfield PCIE_IP.VPD_Request 3 .bitfield PCIE_IP.SramError 4 .bitfield PCIE_IP.PFLR 5 .bitfield PCIE_IP.DataPathReset 6 .bitfield PCIE_IP.OutOfReset 7 .bitfield PCIE_IP.NotInReset 8 .bitfield PCIE_IP.Timeout 9 .bitfield PCIE_IP.VFLR 10 .constant PCIE_IM, PCIE_PF_BASE +0x13001 .constant PCIE_IB, PCIE_PF_BASE +0x13002 .bitfield PCIE_SERDES_CTRL_a.Interrupt 1 .bitfield PCIE_SERDES_CTRL_a.InProgress 2 .bitfield PCIE_SERDES_CTRL_a.InterruptCode 16, 16 .bitfield PCIE_SERDES_CTRL_b.DataWrite 0, 16 .bitfield PCIE_SERDES_CTRL_b.DataRead 16, 16 .constant PCIE_SERDES_CTRL_0a, PCIE_PF_BASE +0x19010 .constant PCIE_SERDES_CTRL_0b, PCIE_SERDES_CTRL_0a +1 .constant PCIE_SERDES_CTRL_1a, PCIE_SERDES_CTRL_0a +2 .constant PCIE_SERDES_CTRL_1b, PCIE_SERDES_CTRL_1a +1 .constant PCIE_SERDES_CTRL_2a, PCIE_SERDES_CTRL_1a +2 .constant PCIE_SERDES_CTRL_2b, PCIE_SERDES_CTRL_2a +1 .constant PCIE_SERDES_CTRL_3a, PCIE_SERDES_CTRL_2a +2 .constant PCIE_SERDES_CTRL_3b, PCIE_SERDES_CTRL_3a +1 .constant PCIE_SERDES_CTRL_4a, PCIE_SERDES_CTRL_3a +2 .constant PCIE_SERDES_CTRL_4b, PCIE_SERDES_CTRL_4a +1 .constant PCIE_SERDES_CTRL_5a, PCIE_SERDES_CTRL_4a +2 .constant PCIE_SERDES_CTRL_5b, PCIE_SERDES_CTRL_5a +1 .constant PCIE_SERDES_CTRL_6a, PCIE_SERDES_CTRL_5a +2 .constant PCIE_SERDES_CTRL_6b, PCIE_SERDES_CTRL_6a +1 .constant PCIE_SERDES_CTRL_7a, PCIE_SERDES_CTRL_6a +2 .constant PCIE_SERDES_CTRL_7b, PCIE_SERDES_CTRL_7a +1