78 lines
3.7 KiB
C
78 lines
3.7 KiB
C
/*****************************************************************************
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* Copyright (c) 2020, rrcc FM10K-Documentation Contributors
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#pragma once
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enum class MgmtRegisters {
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MGMT_SCRATCH_0 = 0x8,
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MGMT_SCRATCH_1 = 0x9,
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SRAM_ERR_IM_0 = 0x448,
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SW_IM = 0x44E,
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BSM_SCRATCH_START = 0x800,
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BSM_SCRATCH_END = 0xBFF,
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BSM_ADDR_OFFSET_0 = 0xC04, // Read-only, 0x000000
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BSM_ADDR_OFFSET_1 = BSM_ADDR_OFFSET_0 + 1,
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BSM_ADDR_OFFSET_2 = BSM_ADDR_OFFSET_0 + 2,
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BSM_ADDR_OFFSET_3 = BSM_ADDR_OFFSET_0 + 3,
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BSM_COUNTER_0 = 0xC08,
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BSM_COUNTER_1 = 0xC09,
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INTERNAL_REGISTER_ALWAYS_00000000 = BSM_ADDR_OFFSET_0, //Read only, set at 0
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INTERNAL_REGISTER_ALWAYS_FFFFFFFF = SRAM_ERR_IM_0, //SRAM_ERR_IM_0 is default two x with 48 1b bits. RW but it's not changed by default. Alternatively SW_IM is also set to 0xFFFFFFFF
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std_SCRATCH_0 = MGMT_SCRATCH_0,
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std_SCRATCH_1 = MGMT_SCRATCH_1,
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std_RETURN_VALUE = BSM_SCRATCH_START + 0x1E0,
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std_RETURN_VALUE_EXTRA = BSM_SCRATCH_START + 0x1E1,
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std_PARAMETER_0 = BSM_SCRATCH_START + 0x1E2,
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std_PARAMETER_1 = BSM_SCRATCH_START + 0x1E3,
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std_EPHEMERAL_REGISTER_0 = BSM_SCRATCH_START + 0x1F0,
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std_EPHEMERAL_REGISTER_1 = std_EPHEMERAL_REGISTER_0 + 0x1,
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std_EPHEMERAL_REGISTER_2 = std_EPHEMERAL_REGISTER_0 + 0x2,
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std_EPHEMERAL_REGISTER_3 = std_EPHEMERAL_REGISTER_0 + 0x3,
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std_EPHEMERAL_REGISTER_4 = std_EPHEMERAL_REGISTER_0 + 0x4,
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std_EPHEMERAL_REGISTER_5 = std_EPHEMERAL_REGISTER_0 + 0x5,
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std_EPHEMERAL_REGISTER_6 = std_EPHEMERAL_REGISTER_0 + 0x6,
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std_EPHEMERAL_REGISTER_7 = std_EPHEMERAL_REGISTER_0 + 0x7,
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std_EPHEMERAL_REGISTER_8 = std_EPHEMERAL_REGISTER_0 + 0x8,
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std_EPHEMERAL_REGISTER_9 = std_EPHEMERAL_REGISTER_0 + 0x9,
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std_EPHEMERAL_REGISTER_10 = std_EPHEMERAL_REGISTER_0 + 0xa,
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std_EPHEMERAL_REGISTER_11 = std_EPHEMERAL_REGISTER_0 + 0xb,
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std_EPHEMERAL_REGISTER_12 = std_EPHEMERAL_REGISTER_0 + 0xc,
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std_EPHEMERAL_REGISTER_13 = std_EPHEMERAL_REGISTER_0 + 0xd,
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std_EPHEMERAL_REGISTER_14 = std_EPHEMERAL_REGISTER_0 + 0xe,
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std_EPHEMERAL_REGISTER_15 = std_EPHEMERAL_REGISTER_0 + 0xf,
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}; |