rrcc/asm/registers.asm

; Definition of registers found on FM10000 ASIP
; Based on Intel datasheet and BSD-3 code.

.constant FATAL_CODE, %0x0
.constant LAST_FATAL_CODE, %0x1

.constant SOFT_RESET, %0x3
.constant DEVICE_CFG, %0x4
.constant RESET_CFG, %0x5
.constant WATCHDOG_CFG, %0x6

.constant MGMT_SCRATCH_0, %0x8
.constant MGMT_SCRATCH_1, MGMT_SCRATCH_0 +1

.constant VITAL_PRODUCT_DATA, %0x304

.constant GLOBAL_INTERRUPT_DETECT_0, %0x400
.constant GLOBAL_INTERRUPT_DETECT_1, %0x401
.constant INTERRUPT_MASK_INT, %0x402

.constant INTERRUPT_MASK_PCIE_0, %0x420
.constant INTERRUPT_MASK_PCIE_1, %0x422
.constant INTERRUPT_MASK_PCIE_2, %0x424
.constant INTERRUPT_MASK_PCIE_3, %0x426
.constant INTERRUPT_MASK_PCIE_4, %0x428
.constant INTERRUPT_MASK_PCIE_5, %0x42a
.constant INTERRUPT_MASK_PCIE_6, %0x42c
.constant INTERRUPT_MASK_PCIE_7, %0x42e
.constant INTERRUPT_MASK_PCIE_8, %0x431

.constant INTERRUPT_MASK_FIBM_0, %0x440
.constant INTERRUPT_MASK_FIBM_1, %0x441
.constant INTERRUPT_MASK_BSM_0, %0x442
.constant INTERRUPT_MASK_BSM_1, %0x443
.constant CORE_INTERRUPT_DETECT, %0x444
.constant CORE_INTERRUPT_MASK, %0x445
.constant SRAM_ERR_IP_0, %0x446
.constant SRAM_ERR_IP_1, %0x447
.constant SRAM_ERR_IM_0, %0x448
.constant SRAM_ERR_IM_1, %0x449
.constant PINS_STAT, %0x44a
.constant PINS_IP, %0x44b
.constant PINS_IM, %0x44c
.constant SW_IP, %0x44d
.constant SW_IM, %0x44e
.constant SW_TEST_AND_SET, %0x44f

.constant LSM_CLKOBS_CTRL, %0x450

.constant CHIP_VERSION, %0x452

.constant BSM_SCRATCH_START, %0x800
.constant BSM_SCRATCH_END, BSM_SCRATCH_START +0x400

.constant BSM_CTRL, %0x000C00
.constant BSM_ARGS, %0x000C01

.constant BSM_ADDR_OFFSET_0, %0x000C04
.constant BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_0 +1
.constant BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_0 +2
.constant BSM_ADDR_OFFSET_3, BSM_ADDR_OFFSET_0 +3

.constant BSM_COUNTER_0, %0x000C08
.constant BSM_COUNTER_1, BSM_COUNTER_0 +1

.constant BSM_SRAM_CTRL, %0x000C0A
.constant BSM_IP, %0x000C0B
.constant BSM_IM, %0x000C0C
.constant PIN_STRAP_STAT, %0x000C0D
.constant FUSE_DATA_0, %0x000C0E
.constant FUSE_DATA_1, %0x000C0F
.constant BIST_CTRL_0, %0x000C10
.constant BIST_CTRL_1, %0x000C11
.constant REI_CTRL, %0x000C12
.constant REI_STAT, %0x000C13

.constant GPIO_CFG, %0x000C15
.constant GPIO_DATA, %0x000C16
.constant GPIO_IP, %0x000C17
.constant GPIO_IM, %0x000C18
.constant I2C_CFG, %0x000C19
.constant I2C_DATA_0, %0x000C1C
.constant I2C_DATA_1, %0x000C1D
.constant I2C_DATA_2, %0x000C1E
.constant I2C_CTRL, %0x000C20
.constant MDIO_CFG, %0x000C22
.constant MDIO_DATA, %0x000C23
.constant MDIO_CTRL, %0x000C24

.constant SPI_TX_DATA, %0x000C26
.constant SPI_RX_DATA, %0x000C27
.constant SPI_HEADER, %0x000C28
.constant SPI_CTRL, %0x000C29

.constant LED_CFG, %0x000C2B
.constant SCAN_DATA_IN, %0x000C2D

.constant CRM_DATA_START, %0x001000 ; 2048 entries, each one 2 words
.constant CRM_DATA_END, %0x001FFF
.constant CRM_CTRL, %0x002000
.constant CRM_STATUS, %0x002001
.constant CRM_TIME, %0x002002

.constant CRM_SRAM_CTRL, %0x002004

.constant CRM_IP, %0x002008

.constant CRM_IM, %0x00200C

.constant CRM_COMMAND_START, %0x002080 ; 64 entries, each one 2 words
.constant CRM_COMMAND_END, %0x0020FF
.constant CRM_REGISTER_START, %0x002100 ; 64 entries, each one 2 words
.constant CRM_REGISTER_END, %0x00217F
.constant CRM_PERIOD_START, %0x002180 ; 64 entries, each one 2 words
.constant CRM_PERIOD_END, %0x0021FF
.constant CRM_PARAM_START, %0x002200 ; 64 entries, each one 1 words
.constant CRM_PARAM_END, %0x002240
.constant PLL_PCIE_CTRL, %0x2241
.constant PLL_PCIE_STAT, %0x2242
.constant SBUS_PCIE_CFG, %0x2243
.constant SBUS_PCIE_COMMAND, %0x2244
.constant SBUS_PCIE_REQUEST, %0x2245
.constant SBUS_PCIE_RESPONSE, %0x2246
.constant SBUS_PCIE_SPICO_IN, %0x2247
.constant SBUS_PCIE_SPICO_OUT, %0x2248
.constant SBUS_PCIE_IP, %0x2249
.constant SBUS_PCIE_IM, %0x224a

.constant SYSTIME_CFG_0, %0x224C
.constant SYSTIME_CFG_1, %0x224D
.constant SYSTIME_0, %0x224E
.constant SYSTIME_1, %0x224F
.constant SYSTIME0_0, %0x2250
.constant SYSTIME0_1, %0x2251
.constant SYSTIME_PULSE_0, %0x2252
.constant SYSTIME_PULSE_1, %0x2253
.constant SYSTIME_CAPTURE_0_0, %0x2254
.constant SYSTIME_CAPTURE_0_1, %0x2255
.constant SYSTIME_CAPTURE_1_0, %0x2256
.constant SYSTIME_CAPTURE_1_1, %0x2257
.constant SYSTIME_CAPTURE_2_0, %0x2258
.constant SYSTIME_CAPTURE_2_1, %0x2259
.constant SYSTIME_CAPTURE_3_0, %0x225a
.constant SYSTIME_CAPTURE_3_1, %0x225b

.constant PCIE_XPLL_CTRL, %0x3000
.constant PCIE_CLK_CTRL, %0x3001
.constant PCIE_CLK_CTRL_2, %0x3002
.constant PCIE_CLKMON_RATIO_CFG, %0x3003
.constant PCIE_CLKMON_TOLERANCE_CFG, %0x3004
.constant PCIE_CLKMON_DEADLINES_CFG, %0x3005
.constant PCIE_CLK_STAT, %0x3006
.constant PCIE_CLK_IP, %0x3007
.constant PCIE_CLK_IM, %0x3008
.constant PCIE_WARM_RESET_DELAY, %0x3009

.constant PORTS_MGMT_BASE_ADDRESS, %0xE8000
.constant PLL_EPL_CTRL, %0xE8000
.constant PLL_EPL_STAT, %0xE8001
.constant PLL_FABRIC_CTRL, %0xE8002
.constant PLL_FABRIC_STAT, %0xE8003
.constant PLL_FABRIC_LOCK, %0xE8004
.constant SBUS_EPL_CFG, %0xE8005
.constant SBUS_EPL_COMMAND, %0xE8006
.constant SBUS_EPL_REQUEST, %0xE8007
.constant SBUS_EPL_RESPONSE, %0xE8008
.constant SBUS_EPL_SPICO_IN, %0xE8009
.constant SBUS_EPL_SPICO_OUT, %0xE800a
.constant SBUS_EPL_IP, %0xE800b
.constant SBUS_EPL_IM, %0xE800c

.constant PM_CLKOBS_CTRL, %0xE8012

; These require offsets to be accessed
.constant PCIE_PF_BASE, %0x100000
.constant PCIE_IB, PCIE_PF_BASE +0x13002
.constant PCIE_SERDES_CTRL_0, PCIE_PF_BASE +0x19010
.constant PCIE_SERDES_CTRL_1, PCIE_SERDES_CTRL_0 +2
.constant PCIE_SERDES_CTRL_2, PCIE_SERDES_CTRL_1 +2
.constant PCIE_SERDES_CTRL_3, PCIE_SERDES_CTRL_2 +2
.constant PCIE_SERDES_CTRL_4, PCIE_SERDES_CTRL_3 +2
.constant PCIE_SERDES_CTRL_5, PCIE_SERDES_CTRL_4 +2
.constant PCIE_SERDES_CTRL_6, PCIE_SERDES_CTRL_5 +2
.constant PCIE_SERDES_CTRL_7, PCIE_SERDES_CTRL_6 +2