Remove zero register from vm bytecode
This commit is contained in:
parent
78b0645034
commit
b72f79a653
SSH key fingerprint:
SHA256:OLTRf6Fl87G52SiR7sWLGNzlJt4WOX+tfI2yxo0z7xk
190
bytecode.go
Normal file
190
bytecode.go
Normal file
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@ -0,0 +1,190 @@
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package randomx
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import (
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"encoding/binary"
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"git.gammaspectra.live/P2Pool/go-randomx/v2/asm"
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"math"
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"math/bits"
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)
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type ByteCodeInstruction struct {
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dst, src byte
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idst, isrc *uint64
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fdst, fsrc *[2]float64
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imm uint64
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simm int64
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Opcode ByteCodeInstructionOp
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target int16
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shift uint8
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memMask uint32
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/*
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union {
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int_reg_t* idst;
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rx_vec_f128* fdst;
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};
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union {
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int_reg_t* isrc;
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rx_vec_f128* fsrc;
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};
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union {
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uint64_t imm;
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int64_t simm;
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};
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InstructionType type;
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union {
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int16_t target;
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uint16_t shift;
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};
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uint32_t memMask;
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*/
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}
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func (i ByteCodeInstruction) getScratchpadSrcAddress() uint64 {
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return (*i.isrc + i.imm) & uint64(i.memMask)
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}
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func (i ByteCodeInstruction) getScratchpadZeroAddress() uint64 {
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return i.imm & uint64(i.memMask)
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}
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func (i ByteCodeInstruction) getScratchpadDestAddress() uint64 {
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return (*i.idst + i.imm) & uint64(i.memMask)
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}
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type ByteCode [RANDOMX_PROGRAM_SIZE]ByteCodeInstruction
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func (c *ByteCode) Interpret(vm *VM) {
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for pc := 0; pc < RANDOMX_PROGRAM_SIZE; pc++ {
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ibc := c[pc]
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switch ibc.Opcode {
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case VM_IADD_RS:
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm
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case VM_IADD_M:
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*ibc.idst += vm.Load64(ibc.getScratchpadSrcAddress())
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case VM_IADD_MZ:
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*ibc.idst += vm.Load64(ibc.getScratchpadZeroAddress())
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case VM_ISUB_R:
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*ibc.idst -= *ibc.isrc
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case VM_ISUB_M:
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*ibc.idst -= vm.Load64(ibc.getScratchpadSrcAddress())
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case VM_ISUB_MZ:
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*ibc.idst -= vm.Load64(ibc.getScratchpadZeroAddress())
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case VM_IMUL_R:
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// also handles imul_rcp
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*ibc.idst *= *ibc.isrc
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case VM_IMUL_M:
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*ibc.idst *= vm.Load64(ibc.getScratchpadSrcAddress())
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case VM_IMUL_MZ:
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*ibc.idst *= vm.Load64(ibc.getScratchpadZeroAddress())
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case VM_IMULH_R:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, *ibc.isrc)
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case VM_IMULH_M:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadSrcAddress()))
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case VM_IMULH_MZ:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadZeroAddress()))
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case VM_ISMULH_R:
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*ibc.idst = smulh(int64(*ibc.idst), int64(*ibc.isrc))
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case VM_ISMULH_M:
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*ibc.idst = smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadSrcAddress())))
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case VM_ISMULH_MZ:
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*ibc.idst = smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadZeroAddress())))
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case VM_INEG_R:
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*ibc.idst = (^(*ibc.idst)) + 1 // 2's complement negative
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case VM_IXOR_R:
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*ibc.idst ^= *ibc.isrc
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case VM_IXOR_M:
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*ibc.idst ^= vm.Load64(ibc.getScratchpadSrcAddress())
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case VM_IXOR_MZ:
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*ibc.idst ^= vm.Load64(ibc.getScratchpadZeroAddress())
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case VM_IROR_R:
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*ibc.idst = bits.RotateLeft64(*ibc.idst, 0-int(*ibc.isrc&63))
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case VM_IROL_R:
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*ibc.idst = bits.RotateLeft64(*ibc.idst, int(*ibc.isrc&63))
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case VM_ISWAP_R:
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*ibc.idst, *ibc.isrc = *ibc.isrc, *ibc.idst
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case VM_FSWAP_R:
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ibc.fdst[HIGH], ibc.fdst[LOW] = ibc.fdst[LOW], ibc.fdst[HIGH]
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case VM_FADD_R:
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ibc.fdst[LOW] += ibc.fsrc[LOW]
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ibc.fdst[HIGH] += ibc.fsrc[HIGH]
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case VM_FADD_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] += lo
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ibc.fdst[HIGH] += hi
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case VM_FSUB_R:
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ibc.fdst[LOW] -= ibc.fsrc[LOW]
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ibc.fdst[HIGH] -= ibc.fsrc[HIGH]
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case VM_FSUB_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] -= lo
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ibc.fdst[HIGH] -= hi
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case VM_FSCAL_R:
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// no dependent on rounding modes
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ibc.fdst[LOW] = math.Float64frombits(math.Float64bits(ibc.fdst[LOW]) ^ 0x80F0000000000000)
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ibc.fdst[HIGH] = math.Float64frombits(math.Float64bits(ibc.fdst[HIGH]) ^ 0x80F0000000000000)
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case VM_FMUL_R:
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ibc.fdst[LOW] *= ibc.fsrc[LOW]
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ibc.fdst[HIGH] *= ibc.fsrc[HIGH]
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case VM_FDIV_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] /= MaskRegisterExponentMantissa(lo, vm.config.eMask[LOW])
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ibc.fdst[HIGH] /= MaskRegisterExponentMantissa(hi, vm.config.eMask[HIGH])
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case VM_FSQRT_R:
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ibc.fdst[LOW] = math.Sqrt(ibc.fdst[LOW])
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ibc.fdst[HIGH] = math.Sqrt(ibc.fdst[HIGH])
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case VM_CBRANCH:
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*ibc.isrc += ibc.imm
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if (*ibc.isrc & uint64(ibc.memMask)) == 0 {
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pc = int(ibc.target)
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}
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case VM_CFROUND:
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tmp := (bits.RotateLeft64(*ibc.isrc, 0-int(ibc.imm))) % 4 // rotate right
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asm.SetRoundingMode(asm.RoundingMode(tmp))
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case VM_ISTORE:
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binary.LittleEndian.PutUint64(vm.ScratchPad[(*ibc.idst+ibc.imm)&uint64(ibc.memMask):], *ibc.isrc)
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case VM_NOP: // we do nothing
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}
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}
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}
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type ByteCodeInstructionOp int
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const (
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VM_NOP = ByteCodeInstructionOp(iota)
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VM_IADD_RS
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VM_IADD_M
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VM_IADD_MZ
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VM_ISUB_R
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VM_ISUB_M
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VM_ISUB_MZ
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VM_IMUL_R
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VM_IMUL_M
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VM_IMUL_MZ
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VM_IMULH_R
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VM_IMULH_M
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VM_IMULH_MZ
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VM_ISMULH_R
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VM_ISMULH_M
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VM_ISMULH_MZ
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VM_IMUL_RCP
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VM_INEG_R
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VM_IXOR_R
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VM_IXOR_M
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VM_IXOR_MZ
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VM_IROR_R
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VM_IROL_R
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VM_ISWAP_R
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VM_FSWAP_R
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VM_FADD_R
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VM_FADD_M
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VM_FSUB_R
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VM_FSUB_M
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VM_FSCAL_R
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VM_FMUL_R
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VM_FDIV_M
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VM_FSQRT_R
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VM_CBRANCH
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VM_CFROUND
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VM_ISTORE
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)
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@ -90,9 +90,6 @@ const CONDITIONOFFSET = RANDOMX_JUMP_OFFSET
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const CONDITIONMASK = ((1 << RANDOMX_JUMP_BITS) - 1)
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const STOREL3CONDITION = 14
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const REGISTERSCOUNT = 8
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const REGISTERCOUNTFLT = 4
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const mantissaSize = 52
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const exponentSize = 11
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const mantissaMask = (uint64(1) << mantissaSize) - 1
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16
register.go
16
register.go
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@ -1,3 +1,17 @@
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package randomx
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type RegisterLine [REGISTERSCOUNT]uint64
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const RegistersCount = 8
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const RegistersCountFloat = 4
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type RegisterLine [RegistersCount]uint64
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type RegisterFile struct {
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r RegisterLine
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f [RegistersCountFloat][2]float64
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e [RegistersCountFloat][2]float64
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a [RegistersCountFloat][2]float64
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}
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type MemoryRegisters struct {
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mx, ma uint64
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}
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@ -85,8 +85,8 @@ func generateSuperscalarCode(scalarProgram SuperScalarProgram) ProgramFunc {
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for i := range p {
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instr := &p[i]
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dst := instr.Dst_Reg % REGISTERSCOUNT
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src := instr.Src_Reg % REGISTERSCOUNT
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dst := instr.Dst_Reg % RegistersCount
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src := instr.Src_Reg % RegistersCount
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switch instr.Opcode {
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case S_ISUB_R:
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30
vm.go
30
vm.go
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@ -49,13 +49,13 @@ type VM struct {
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Prog []byte
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ScratchPad [ScratchpadSize]byte
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ByteCode [RANDOMX_PROGRAM_SIZE]InstructionByteCode
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ByteCode ByteCode
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// program configuration see program.hpp
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entropy [16]uint64
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reg REGISTER_FILE // the register file
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reg RegisterFile // the register file
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mem MemoryRegisters
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config Config // configuration
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datasetOffset uint64
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@ -75,16 +75,6 @@ type Config struct {
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readReg [4]uint64
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}
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type REGISTER_FILE struct {
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r RegisterLine
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f [4][2]float64
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e [4][2]float64
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a [4][2]float64
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}
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type MemoryRegisters struct {
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mx, ma uint64
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}
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const LOW = 0
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const HIGH = 1
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@ -120,7 +110,7 @@ func (vm *VM) Run(input_hash [64]byte) {
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vm.config.eMask[LOW] = getFloatMask(vm.entropy[14])
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vm.config.eMask[HIGH] = getFloatMask(vm.entropy[15])
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vm.Compile_TO_Bytecode()
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vm.CompileToBytecode()
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spAddr0 := vm.mem.mx
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spAddr1 := vm.mem.ma
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@ -135,23 +125,23 @@ func (vm *VM) Run(input_hash [64]byte) {
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spAddr1 ^= spMix >> 32
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spAddr1 &= ScratchpadL3Mask64
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for i := uint64(0); i < REGISTERSCOUNT; i++ {
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for i := uint64(0); i < RegistersCount; i++ {
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vm.reg.r[i] ^= vm.Load64(spAddr0 + 8*i)
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}
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for i := uint64(0); i < REGISTERCOUNTFLT; i++ {
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.f[i] = vm.Load32FA(spAddr1 + 8*i)
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}
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for i := uint64(0); i < REGISTERCOUNTFLT; i++ {
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vm.reg.e[i] = vm.Load32FA(spAddr1 + 8*(i+REGISTERCOUNTFLT))
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.e[i] = vm.Load32FA(spAddr1 + 8*(i+RegistersCountFloat))
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vm.reg.e[i][LOW] = MaskRegisterExponentMantissa(vm.reg.e[i][LOW], vm.config.eMask[LOW])
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vm.reg.e[i][HIGH] = MaskRegisterExponentMantissa(vm.reg.e[i][HIGH], vm.config.eMask[HIGH])
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}
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// todo: pass register file directly!
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vm.InterpretByteCode()
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vm.ByteCode.Interpret(vm)
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vm.mem.mx ^= vm.reg.r[vm.config.readReg[2]] ^ vm.reg.r[vm.config.readReg[3]]
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vm.mem.mx &= CacheLineAlignMask
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@ -163,11 +153,11 @@ func (vm *VM) Run(input_hash [64]byte) {
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// swap the elements
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vm.mem.mx, vm.mem.ma = vm.mem.ma, vm.mem.mx
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for i := uint64(0); i < REGISTERSCOUNT; i++ {
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for i := uint64(0); i < RegistersCount; i++ {
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binary.LittleEndian.PutUint64(vm.ScratchPad[spAddr1+8*i:], vm.reg.r[i])
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}
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for i := uint64(0); i < REGISTERCOUNTFLT; i++ {
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.f[i][LOW] = math.Float64frombits(math.Float64bits(vm.reg.f[i][LOW]) ^ math.Float64bits(vm.reg.e[i][LOW]))
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vm.reg.f[i][HIGH] = math.Float64frombits(math.Float64bits(vm.reg.f[i][HIGH]) ^ math.Float64bits(vm.reg.e[i][HIGH]))
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@ -30,17 +30,12 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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package randomx
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import (
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"git.gammaspectra.live/P2Pool/go-randomx/v2/asm"
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"math"
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"math/bits"
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"unsafe"
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)
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import "encoding/binary"
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//reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#51-instruction-encoding
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var Zero uint64 = 0
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// since go does not have union, use byte array
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type VM_Instruction []byte // it is hardcode 8 bytes
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@ -60,80 +55,11 @@ func (ins VM_Instruction) Opcode() byte {
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return ins[0]
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}
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type VM_Instruction_Type int
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const (
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VM_IADD_RS VM_Instruction_Type = 0
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VM_IADD_M VM_Instruction_Type = 1
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VM_ISUB_R VM_Instruction_Type = 2
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VM_ISUB_M VM_Instruction_Type = 3
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VM_IMUL_R VM_Instruction_Type = 4
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VM_IMUL_M VM_Instruction_Type = 5
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VM_IMULH_R VM_Instruction_Type = 6
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VM_IMULH_M VM_Instruction_Type = 7
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VM_ISMULH_R VM_Instruction_Type = 8
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VM_ISMULH_M VM_Instruction_Type = 9
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VM_IMUL_RCP VM_Instruction_Type = 10
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VM_INEG_R VM_Instruction_Type = 11
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VM_IXOR_R VM_Instruction_Type = 12
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VM_IXOR_M VM_Instruction_Type = 13
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VM_IROR_R VM_Instruction_Type = 14
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VM_IROL_R VM_Instruction_Type = 15
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VM_ISWAP_R VM_Instruction_Type = 16
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VM_FSWAP_R VM_Instruction_Type = 17
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VM_FADD_R VM_Instruction_Type = 18
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VM_FADD_M VM_Instruction_Type = 19
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VM_FSUB_R VM_Instruction_Type = 20
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VM_FSUB_M VM_Instruction_Type = 21
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VM_FSCAL_R VM_Instruction_Type = 22
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VM_FMUL_R VM_Instruction_Type = 23
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VM_FDIV_M VM_Instruction_Type = 24
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VM_FSQRT_R VM_Instruction_Type = 25
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VM_CBRANCH VM_Instruction_Type = 26
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VM_CFROUND VM_Instruction_Type = 27
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VM_ISTORE VM_Instruction_Type = 28
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VM_NOP VM_Instruction_Type = 29
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)
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var Names = map[VM_Instruction_Type]string{
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VM_IADD_RS: "VM_IADD_RS",
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VM_IADD_M: "VM_IADD_M",
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VM_ISUB_R: "VM_ISUB_R",
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VM_ISUB_M: "VM_ISUB_M",
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VM_IMUL_R: "VM_IMUL_R",
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VM_IMUL_M: "VM_IMUL_M",
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VM_IMULH_R: "VM_IMULH_R",
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VM_IMULH_M: "VM_IMULH_M",
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VM_ISMULH_R: "VM_ISMULH_R",
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VM_ISMULH_M: "VM_ISMULH_M",
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VM_IMUL_RCP: "VM_IMUL_RCP",
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VM_INEG_R: "VM_INEG_R",
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VM_IXOR_R: "VM_IXOR_R",
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VM_IXOR_M: "VM_IXOR_M",
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VM_IROR_R: "VM_IROR_R",
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VM_IROL_R: "VM_IROL_R",
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VM_ISWAP_R: "VM_ISWAP_R",
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VM_FSWAP_R: "VM_FSWAP_R",
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VM_FADD_R: "VM_FADD_R",
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VM_FADD_M: "VM_FADD_M",
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VM_FSUB_R: "VM_FSUB_R",
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VM_FSUB_M: "VM_FSUB_M",
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VM_FSCAL_R: "VM_FSCAL_R",
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VM_FMUL_R: "VM_FMUL_R",
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VM_FDIV_M: "VM_FDIV_M",
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VM_FSQRT_R: "VM_FSQRT_R",
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VM_CBRANCH: "VM_CBRANCH",
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VM_CFROUND: "VM_CFROUND",
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VM_ISTORE: "VM_ISTORE",
|
||||
VM_NOP: "VM_NOP",
|
||||
}
|
||||
|
||||
// this will interpret single vm instruction
|
||||
// CompileToBytecode this will interpret single vm instruction
|
||||
// reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#52-integer-instructions
|
||||
func (vm *VM) Compile_TO_Bytecode() {
|
||||
func (vm *VM) CompileToBytecode() {
|
||||
|
||||
var registerUsage [REGISTERSCOUNT]int
|
||||
var registerUsage [RegistersCount]int
|
||||
for i := range registerUsage {
|
||||
registerUsage[i] = -1
|
||||
}
|
||||
|
|
@ -143,8 +69,8 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc := &vm.ByteCode[i]
|
||||
|
||||
opcode := instr.Opcode()
|
||||
dst := instr.Dst() % REGISTERSCOUNT // bit shift optimization
|
||||
src := instr.Src() % REGISTERSCOUNT
|
||||
dst := instr.Dst() % RegistersCount // bit shift optimization
|
||||
src := instr.Src() % RegistersCount
|
||||
ibc.dst = dst
|
||||
ibc.src = src
|
||||
switch opcode {
|
||||
|
|
@ -174,7 +100,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_IADD_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -202,7 +128,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_ISUB_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -230,7 +156,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_IMUL_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -251,7 +177,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_IMULH_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -272,7 +198,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_ISMULH_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -316,7 +242,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.memMask = ScratchpadL2Mask
|
||||
}
|
||||
} else {
|
||||
ibc.isrc = &Zero
|
||||
ibc.Opcode = VM_IXOR_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
|
@ -360,20 +286,20 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
// below are floating point instructions
|
||||
case 120, 121, 122, 123: // 4
|
||||
ibc.Opcode = VM_FSWAP_R
|
||||
if dst < REGISTERCOUNTFLT {
|
||||
if dst < RegistersCountFloat {
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
} else {
|
||||
ibc.fdst = &vm.reg.e[dst-REGISTERCOUNTFLT]
|
||||
ibc.fdst = &vm.reg.e[dst-RegistersCountFloat]
|
||||
}
|
||||
case 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139: //16
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
src := instr.Src() % REGISTERCOUNTFLT
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FADD_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
|
||||
case 140, 141, 142, 143, 144: //5
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FADD_M
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
|
|
@ -385,13 +311,13 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
|
||||
case 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160: //16
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
src := instr.Src() % REGISTERCOUNTFLT
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FSUB_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
case 161, 162, 163, 164, 165: //5
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSUB_M
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
|
|
@ -403,17 +329,17 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
|
||||
case 166, 167, 168, 169, 170, 171: //6
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSCAL_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
case 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203: //32
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
src := instr.Src() % REGISTERCOUNTFLT
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FMUL_R
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
case 204, 205, 206, 207: //4
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FDIV_M
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
|
|
@ -424,13 +350,13 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
}
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
case 208, 209, 210, 211, 212, 213: //6
|
||||
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSQRT_R
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
|
||||
case 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238: //25 // CBRANCH and CFROUND are interchanged
|
||||
ibc.Opcode = VM_CBRANCH
|
||||
reg := instr.Dst() % REGISTERSCOUNT
|
||||
reg := instr.Dst() % RegistersCount
|
||||
ibc.isrc = &vm.reg.r[reg]
|
||||
ibc.target = int16(registerUsage[reg])
|
||||
shift := uint64(instr.Mod()>>4) + CONDITIONOFFSET
|
||||
|
|
@ -441,7 +367,7 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
}
|
||||
ibc.memMask = CONDITIONMASK << shift
|
||||
|
||||
for j := 0; j < REGISTERSCOUNT; j++ {
|
||||
for j := 0; j < RegistersCount; j++ {
|
||||
registerUsage[j] = i
|
||||
}
|
||||
|
||||
|
|
@ -474,47 +400,6 @@ func (vm *VM) Compile_TO_Bytecode() {
|
|||
|
||||
}
|
||||
|
||||
type InstructionByteCode struct {
|
||||
dst, src byte
|
||||
idst, isrc *uint64
|
||||
fdst, fsrc *[2]float64
|
||||
imm uint64
|
||||
simm int64
|
||||
Opcode VM_Instruction_Type
|
||||
target int16
|
||||
shift uint8
|
||||
memMask uint32
|
||||
/*
|
||||
union {
|
||||
int_reg_t* idst;
|
||||
rx_vec_f128* fdst;
|
||||
};
|
||||
union {
|
||||
int_reg_t* isrc;
|
||||
rx_vec_f128* fsrc;
|
||||
};
|
||||
union {
|
||||
uint64_t imm;
|
||||
int64_t simm;
|
||||
};
|
||||
InstructionType type;
|
||||
union {
|
||||
int16_t target;
|
||||
uint16_t shift;
|
||||
};
|
||||
uint32_t memMask;
|
||||
*/
|
||||
|
||||
}
|
||||
|
||||
func (ibc *InstructionByteCode) getScratchpadAddress() uint64 {
|
||||
return (*ibc.isrc + ibc.imm) & uint64(ibc.memMask)
|
||||
}
|
||||
|
||||
func (ibc *InstructionByteCode) getScratchpadDestAddress() uint64 {
|
||||
return (*ibc.idst + ibc.imm) & uint64(ibc.memMask)
|
||||
}
|
||||
|
||||
func (vm *VM) Load64(addr uint64) uint64 {
|
||||
return *(*uint64)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
}
|
||||
|
|
@ -531,85 +416,3 @@ func (vm *VM) Load32FA(addr uint64) [2]float64 {
|
|||
a := *(*[2]int32)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
return [2]float64{float64(a[LOW]), float64(a[HIGH])}
|
||||
}
|
||||
|
||||
func (vm *VM) InterpretByteCode() {
|
||||
for pc := 0; pc < RANDOMX_PROGRAM_SIZE; pc++ {
|
||||
ibc := &vm.ByteCode[pc]
|
||||
switch ibc.Opcode {
|
||||
case VM_IADD_RS:
|
||||
*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm
|
||||
case VM_IADD_M:
|
||||
*ibc.idst += vm.Load64(ibc.getScratchpadAddress())
|
||||
case VM_ISUB_R:
|
||||
*ibc.idst -= *ibc.isrc
|
||||
case VM_ISUB_M:
|
||||
*ibc.idst -= vm.Load64(ibc.getScratchpadAddress())
|
||||
case VM_IMUL_R:
|
||||
// also handles imul_rcp
|
||||
*ibc.idst *= *ibc.isrc
|
||||
case VM_IMUL_M:
|
||||
*ibc.idst *= vm.Load64(ibc.getScratchpadAddress())
|
||||
case VM_IMULH_R:
|
||||
*ibc.idst, _ = bits.Mul64(*ibc.idst, *ibc.isrc)
|
||||
case VM_IMULH_M:
|
||||
*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadAddress()))
|
||||
case VM_ISMULH_R:
|
||||
*ibc.idst = smulh(int64(*ibc.idst), int64(*ibc.isrc))
|
||||
case VM_ISMULH_M:
|
||||
*ibc.idst = smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadAddress())))
|
||||
case VM_INEG_R:
|
||||
*ibc.idst = (^(*ibc.idst)) + 1 // 2's complement negative
|
||||
case VM_IXOR_R:
|
||||
*ibc.idst ^= *ibc.isrc
|
||||
case VM_IXOR_M:
|
||||
*ibc.idst ^= vm.Load64(ibc.getScratchpadAddress())
|
||||
case VM_IROR_R:
|
||||
*ibc.idst = bits.RotateLeft64(*ibc.idst, 0-int(*ibc.isrc&63))
|
||||
case VM_IROL_R:
|
||||
*ibc.idst = bits.RotateLeft64(*ibc.idst, int(*ibc.isrc&63))
|
||||
case VM_ISWAP_R:
|
||||
*ibc.idst, *ibc.isrc = *ibc.isrc, *ibc.idst
|
||||
case VM_FSWAP_R:
|
||||
ibc.fdst[HIGH], ibc.fdst[LOW] = ibc.fdst[LOW], ibc.fdst[HIGH]
|
||||
case VM_FADD_R:
|
||||
ibc.fdst[LOW] += ibc.fsrc[LOW]
|
||||
ibc.fdst[HIGH] += ibc.fsrc[HIGH]
|
||||
case VM_FADD_M:
|
||||
lo, hi := vm.Load32F(ibc.getScratchpadAddress())
|
||||
ibc.fdst[LOW] += lo
|
||||
ibc.fdst[HIGH] += hi
|
||||
case VM_FSUB_R:
|
||||
ibc.fdst[LOW] -= ibc.fsrc[LOW]
|
||||
ibc.fdst[HIGH] -= ibc.fsrc[HIGH]
|
||||
case VM_FSUB_M:
|
||||
lo, hi := vm.Load32F(ibc.getScratchpadAddress())
|
||||
ibc.fdst[LOW] -= lo
|
||||
ibc.fdst[HIGH] -= hi
|
||||
case VM_FSCAL_R:
|
||||
// no dependent on rounding modes
|
||||
ibc.fdst[LOW] = math.Float64frombits(math.Float64bits(ibc.fdst[LOW]) ^ 0x80F0000000000000)
|
||||
ibc.fdst[HIGH] = math.Float64frombits(math.Float64bits(ibc.fdst[HIGH]) ^ 0x80F0000000000000)
|
||||
case VM_FMUL_R:
|
||||
ibc.fdst[LOW] *= ibc.fsrc[LOW]
|
||||
ibc.fdst[HIGH] *= ibc.fsrc[HIGH]
|
||||
case VM_FDIV_M:
|
||||
lo, hi := vm.Load32F(ibc.getScratchpadAddress())
|
||||
ibc.fdst[LOW] /= MaskRegisterExponentMantissa(lo, vm.config.eMask[LOW])
|
||||
ibc.fdst[HIGH] /= MaskRegisterExponentMantissa(hi, vm.config.eMask[HIGH])
|
||||
case VM_FSQRT_R:
|
||||
ibc.fdst[LOW] = math.Sqrt(ibc.fdst[LOW])
|
||||
ibc.fdst[HIGH] = math.Sqrt(ibc.fdst[HIGH])
|
||||
case VM_CBRANCH:
|
||||
*ibc.isrc += ibc.imm
|
||||
if (*ibc.isrc & uint64(ibc.memMask)) == 0 {
|
||||
pc = int(ibc.target)
|
||||
}
|
||||
case VM_CFROUND:
|
||||
tmp := (bits.RotateLeft64(*ibc.isrc, 0-int(ibc.imm))) % 4 // rotate right
|
||||
asm.SetRoundingMode(asm.RoundingMode(tmp))
|
||||
case VM_ISTORE:
|
||||
binary.LittleEndian.PutUint64(vm.ScratchPad[(*ibc.idst+ibc.imm)&uint64(ibc.memMask):], *ibc.isrc)
|
||||
case VM_NOP: // we do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue