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649 lines
16 KiB
Go
649 lines
16 KiB
Go
/*
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Copyright (c) 2019 DERO Foundation. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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package randomx
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import (
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"git.gammaspectra.live/P2Pool/go-randomx/v3/internal/blake2"
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"math/bits"
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)
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type ExecutionPort byte
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const (
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Null ExecutionPort = iota
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P0 = 1
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P1 = 2
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P5 = 4
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P01 = P0 | P1
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P05 = P0 | P5
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P015 = P0 | P1 | P5
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)
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type MacroOP struct {
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Name string
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Size int
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Latency int
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UOP1 ExecutionPort
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UOP2 ExecutionPort
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Dependent bool
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}
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func (m *MacroOP) GetSize() int {
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return m.Size
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}
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func (m *MacroOP) GetLatency() int {
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return m.Latency
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}
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func (m *MacroOP) GetUOP1() ExecutionPort {
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return m.UOP1
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}
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func (m *MacroOP) GetUOP2() ExecutionPort {
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return m.UOP2
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}
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func (m *MacroOP) IsSimple() bool {
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return m.UOP2 == Null
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}
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func (m *MacroOP) IsEliminated() bool {
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return m.UOP1 == Null
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}
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func (m *MacroOP) IsDependent() bool {
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return m.Dependent
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}
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// 3 byte instructions
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var M_Add_rr = MacroOP{"add r,r", 3, 1, P015, Null, false}
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var M_Sub_rr = MacroOP{"sub r,r", 3, 1, P015, Null, false}
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var M_Xor_rr = MacroOP{"xor r,r", 3, 1, P015, Null, false}
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var M_Imul_r = MacroOP{"imul r", 3, 4, P1, P5, false}
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var M_Mul_r = MacroOP{"mul r", 3, 4, P1, P5, false}
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var M_Mov_rr = MacroOP{"mov r,r", 3, 0, Null, Null, false}
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// latency is 1 lower
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var M_Imul_r_dependent = MacroOP{"imul r", 3, 3, P1, Null, true} // this is the dependent version where current instruction depends on previous instruction
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// Size: 4 bytes
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var M_Lea_SIB = MacroOP{"lea r,r+r*s", 4, 1, P01, Null, false}
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var M_Imul_rr = MacroOP{"imul r,r", 4, 3, P1, Null, false}
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var M_Ror_ri = MacroOP{"ror r,i", 4, 1, P05, Null, false}
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// Size: 7 bytes (can be optionally padded with nop to 8 or 9 bytes)
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var M_Add_ri = MacroOP{"add r,i", 7, 1, P015, Null, false}
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var M_Xor_ri = MacroOP{"xor r,i", 7, 1, P015, Null, false}
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// Size: 10 bytes
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var M_Mov_ri64 = MacroOP{"mov rax,i64", 10, 1, P015, Null, false}
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// unused are not implemented
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type Instruction struct {
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Opcode byte
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UOP MacroOP
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SrcOP int
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ResultOP int
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DstOP int
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UOP_Array []MacroOP
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}
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func (ins *Instruction) GetUOPCount() int {
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if len(ins.UOP_Array) != 0 {
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return len(ins.UOP_Array)
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} else {
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// NOP
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if ins.Opcode == S_NOP { // nop is assumed to be zero bytes
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return 0
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}
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return 1
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}
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}
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func (ins *Instruction) GetSize() int {
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if len(ins.UOP_Array) != 0 {
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sum_size := 0
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for i := range ins.UOP_Array {
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sum_size += ins.UOP_Array[i].GetSize()
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}
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return sum_size
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} else {
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return ins.UOP.GetSize()
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}
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}
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func (ins *Instruction) IsSimple() bool {
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if ins.GetSize() == 1 {
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return true
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}
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return false
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}
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func (ins *Instruction) GetLatency() int {
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if len(ins.UOP_Array) != 0 {
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sum := 0
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for i := range ins.UOP_Array {
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sum += ins.UOP_Array[i].GetLatency()
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}
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return sum
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} else {
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return ins.UOP.GetLatency()
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}
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}
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const (
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S_INVALID = 0xFF
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S_NOP = 0xFE
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S_ISUB_R = 0
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S_IXOR_R = 1
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S_IADD_RS = 2
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S_IMUL_R = 3
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S_IROR_C = 4
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S_IADD_C7 = 5
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S_IXOR_C7 = 6
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S_IADD_C8 = 7
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S_IXOR_C8 = 8
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S_IADD_C9 = 9
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S_IXOR_C9 = 10
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S_IMULH_R = 11
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S_ISMULH_R = 12
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S_IMUL_RCP = 13
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)
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// SrcOP/DstOp are used to selected registers
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var ISUB_R = Instruction{Opcode: S_ISUB_R, UOP: M_Sub_rr, SrcOP: 0}
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var IXOR_R = Instruction{Opcode: S_IXOR_R, UOP: M_Xor_rr, SrcOP: 0}
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var IADD_RS = Instruction{Opcode: S_IADD_RS, UOP: M_Lea_SIB, SrcOP: 0}
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var IMUL_R = Instruction{Opcode: S_IMUL_R, UOP: M_Imul_rr, SrcOP: 0}
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var IROR_C = Instruction{Opcode: S_IROR_C, UOP: M_Ror_ri, SrcOP: -1}
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var IADD_C7 = Instruction{Opcode: S_IADD_C7, UOP: M_Add_ri, SrcOP: -1}
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var IXOR_C7 = Instruction{Opcode: S_IXOR_C7, UOP: M_Xor_ri, SrcOP: -1}
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var IADD_C8 = Instruction{Opcode: S_IADD_C8, UOP: M_Add_ri, SrcOP: -1}
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var IXOR_C8 = Instruction{Opcode: S_IXOR_C8, UOP: M_Xor_ri, SrcOP: -1}
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var IADD_C9 = Instruction{Opcode: S_IADD_C9, UOP: M_Add_ri, SrcOP: -1}
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var IXOR_C9 = Instruction{Opcode: S_IXOR_C9, UOP: M_Xor_ri, SrcOP: -1}
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var IMULH_R = Instruction{Opcode: S_IMULH_R, UOP_Array: []MacroOP{M_Mov_rr, M_Mul_r, M_Mov_rr}, ResultOP: 1, DstOP: 0, SrcOP: 1}
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var ISMULH_R = Instruction{Opcode: S_ISMULH_R, UOP_Array: []MacroOP{M_Mov_rr, M_Imul_r, M_Mov_rr}, ResultOP: 1, DstOP: 0, SrcOP: 1}
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var IMUL_RCP = Instruction{Opcode: S_IMUL_RCP, UOP_Array: []MacroOP{M_Mov_ri64, M_Imul_r_dependent}, ResultOP: 1, DstOP: 1, SrcOP: -1}
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// how random 16 bytes are split into instructions
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var buffer0 = []int{4, 8, 4}
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var buffer1 = []int{7, 3, 3, 3}
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var buffer2 = []int{3, 7, 3, 3}
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var buffer3 = []int{4, 9, 3}
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var buffer4 = []int{4, 4, 4, 4}
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var buffer5 = []int{3, 3, 10}
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var decoderToInstructionSize = [][]int{
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buffer0,
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buffer1,
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buffer2,
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buffer3,
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buffer4,
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buffer5,
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}
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type DecoderType int
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const Decoder484 DecoderType = 0
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const Decoder7333 DecoderType = 1
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const Decoder3733 DecoderType = 2
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const Decoder493 DecoderType = 3
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const Decoder4444 DecoderType = 4
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const Decoder3310 DecoderType = 5
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func (d DecoderType) GetSize() int {
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switch d {
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case Decoder484:
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return 3
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case Decoder7333:
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return 4
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case Decoder3733:
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return 4
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case Decoder493:
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return 3
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case Decoder4444:
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return 4
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case Decoder3310:
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return 3
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default:
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panic("unknown decoder")
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}
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}
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func (d DecoderType) String() string {
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switch d {
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case Decoder484:
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return "Decoder484"
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case Decoder7333:
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return "Decoder7333"
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case Decoder3733:
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return "Decoder3733"
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case Decoder493:
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return "Decoder493"
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case Decoder4444:
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return "Decoder4444"
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case Decoder3310:
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return "Decoder3310"
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default:
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panic("unknown decoder")
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}
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}
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func FetchNextDecoder(ins *Instruction, cycle int, mulcount int, gen *blake2.Generator) DecoderType {
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if ins.Opcode == S_IMULH_R || ins.Opcode == S_ISMULH_R {
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return Decoder3310
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}
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// make sure multiplication port is satured, if number of multiplications les less than number of cycles, a 4444 is returned
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if mulcount < (cycle + 1) {
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return Decoder4444
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}
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if ins.Opcode == S_IMUL_RCP {
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if gen.GetByte()&1 == 1 {
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return Decoder484
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} else {
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return Decoder493
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}
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}
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// we are here means selecta decoded randomly
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rnd_byte := gen.GetByte()
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switch rnd_byte & 3 {
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case 0:
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return Decoder484
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case 1:
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return Decoder7333
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case 2:
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return Decoder3733
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case 3:
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return Decoder493
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}
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panic("can never reach")
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return Decoder484
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}
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type SuperScalarProgram []SuperScalarInstruction
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func (p SuperScalarProgram) setAddressRegister(addressRegister uint8) {
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p[0].Dst = addressRegister
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}
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func (p SuperScalarProgram) AddressRegister() uint8 {
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return p[0].Dst
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}
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func (p SuperScalarProgram) Program() []SuperScalarInstruction {
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return p[1:]
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}
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func BuildSuperScalarProgram(gen *blake2.Generator) SuperScalarProgram {
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cycle := 0
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depcycle := 0
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//retire_cycle := 0
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mulcount := 0
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ports_saturated := false
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program_size := 0
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//current_instruction := INOP
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macro_op_index := 0
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macro_op_count := 0
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throwAwayCount := 0
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code_size := 0
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program := make(SuperScalarProgram, 1, 512)
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var registers [8]Register
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sins := &SuperScalarInstruction{}
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sins.ins = &Instruction{Opcode: S_NOP}
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portbusy := make([][]int, CYCLE_MAP_SIZE)
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for i := range portbusy {
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portbusy[i] = make([]int, 3)
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}
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done := 0
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for decode_cycle := 0; decode_cycle < RANDOMX_SUPERSCALAR_LATENCY && !ports_saturated && program_size < SuperscalarMaxSize; decode_cycle++ {
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decoder := FetchNextDecoder(sins.ins, decode_cycle, mulcount, gen)
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if cycle == 51 {
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// break
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}
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buffer_index := 0
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for buffer_index < decoder.GetSize() { // generate instructions for the current decoder
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top_cycle := cycle
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if macro_op_index >= sins.ins.GetUOPCount() {
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if ports_saturated || program_size >= SuperscalarMaxSize {
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break
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}
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CreateSuperScalarInstruction(sins, gen, decoderToInstructionSize[decoder][buffer_index], decoder, len(decoderToInstructionSize[decoder]) == (buffer_index+1), buffer_index == 0)
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macro_op_index = 0
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}
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mop := sins.ins.UOP
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if sins.ins.GetUOPCount() == 1 {
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} else {
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mop = sins.ins.UOP_Array[macro_op_index]
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}
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//calculate the earliest cycle when this macro-op (all of its uOPs) can be scheduled for execution
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scheduleCycle := ScheduleMop(&mop, portbusy, cycle, depcycle, false)
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if scheduleCycle < 0 {
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ports_saturated = true
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break
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}
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if macro_op_index == sins.ins.SrcOP { // FIXME
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forward := 0
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for ; forward < LOOK_FORWARD_CYCLES && !sins.SelectSource(scheduleCycle, ®isters, gen); forward++ {
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scheduleCycle++
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cycle++
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}
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if forward == LOOK_FORWARD_CYCLES {
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if throwAwayCount < MAX_THROWAWAY_COUNT {
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throwAwayCount++
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macro_op_index = sins.ins.GetUOPCount()
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continue
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}
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break
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}
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}
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if macro_op_index == sins.ins.DstOP { // FIXME
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forward := 0
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for ; forward < LOOK_FORWARD_CYCLES && !sins.SelectDestination(scheduleCycle, throwAwayCount > 0, ®isters, gen); forward++ {
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scheduleCycle++
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cycle++
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}
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if forward == LOOK_FORWARD_CYCLES {
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if throwAwayCount < MAX_THROWAWAY_COUNT {
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throwAwayCount++
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macro_op_index = sins.ins.GetUOPCount()
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continue
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}
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break
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}
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}
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throwAwayCount = 0
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// recalculate when the instruction can be scheduled based on operand availability
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scheduleCycle = ScheduleMop(&mop, portbusy, scheduleCycle, scheduleCycle, true)
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depcycle = scheduleCycle + mop.GetLatency() // calculate when will the result be ready
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if macro_op_index == sins.ins.ResultOP { // fix me
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registers[sins.Dst].Latency = depcycle
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registers[sins.Dst].LastOpGroup = sins.OpGroup
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registers[sins.Dst].LastOpPar = sins.OpGroupPar
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}
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code_size += mop.GetSize()
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buffer_index++
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macro_op_index++
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macro_op_count++
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// terminating condition for 99% case
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if scheduleCycle >= RANDOMX_SUPERSCALAR_LATENCY {
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ports_saturated = true
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}
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cycle = top_cycle
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// when all uops of current instruction have been issued, add the instruction to superscalar program
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if macro_op_index >= sins.ins.GetUOPCount() {
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sins.FixSrcReg() // fix src register once and for all
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program = append(program, *sins)
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if sins.ins.Opcode == S_IMUL_R || sins.ins.Opcode == S_IMULH_R || sins.ins.Opcode == S_ISMULH_R || sins.ins.Opcode == S_IMUL_RCP {
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mulcount++
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}
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}
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done++
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}
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cycle++
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}
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var asic_latencies [8]int
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for i := range program {
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if i == 0 {
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continue
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}
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lastdst := asic_latencies[program[i].Dst] + 1
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lastsrc := 0
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if program[i].Dst != program[i].Src {
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lastsrc = asic_latencies[program[i].Src] + 1
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}
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asic_latencies[program[i].Dst] = max(lastdst, lastsrc)
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}
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asic_latency_max := 0
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address_reg := 0
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for i := range asic_latencies {
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if asic_latencies[i] > asic_latency_max {
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asic_latency_max = asic_latencies[i]
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address_reg = i
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}
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}
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// Set AddressRegister hack
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program.setAddressRegister(uint8(address_reg))
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return program
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}
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const CYCLE_MAP_SIZE int = RANDOMX_SUPERSCALAR_LATENCY + 4
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const LOOK_FORWARD_CYCLES int = 4
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const MAX_THROWAWAY_COUNT int = 256
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// ScheduleUop schedule the uop as early as possible
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func ScheduleUop(uop ExecutionPort, portbusy [][]int, cycle int, commit bool) int {
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for ; cycle < CYCLE_MAP_SIZE; cycle++ { // since cycle is value based, its restored on return
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if (uop&P5) != 0 && portbusy[cycle][2] == 0 {
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if commit {
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portbusy[cycle][2] = int(uop)
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}
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return cycle
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}
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if (uop&P0) != 0 && portbusy[cycle][0] == 0 {
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if commit {
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portbusy[cycle][0] = int(uop)
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}
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return cycle
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}
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if (uop&P1) != 0 && portbusy[cycle][1] == 0 {
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if commit {
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portbusy[cycle][1] = int(uop)
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}
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return cycle
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}
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}
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return -1
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}
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func ScheduleMop(mop *MacroOP, portbusy [][]int, cycle int, depcycle int, commit bool) int {
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if mop.IsDependent() {
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cycle = max(cycle, depcycle)
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}
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if mop.IsEliminated() {
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|
return cycle
|
|
} else if mop.IsSimple() {
|
|
return ScheduleUop(mop.GetUOP1(), portbusy, cycle, commit)
|
|
} else {
|
|
for ; cycle < CYCLE_MAP_SIZE; cycle++ { // since cycle is value based, its restored on return
|
|
cycle1 := ScheduleUop(mop.GetUOP1(), portbusy, cycle, false)
|
|
cycle2 := ScheduleUop(mop.GetUOP2(), portbusy, cycle, false)
|
|
|
|
if cycle1 == cycle2 {
|
|
if commit {
|
|
ScheduleUop(mop.GetUOP1(), portbusy, cycle, true)
|
|
ScheduleUop(mop.GetUOP2(), portbusy, cycle, true)
|
|
}
|
|
return cycle1
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -1
|
|
}
|
|
|
|
type Register struct {
|
|
Value uint64
|
|
Latency int
|
|
LastOpGroup int
|
|
LastOpPar int //-1 = immediate , 0 to 7 register
|
|
Status int // can be RegisterNeedsDisplacement = 5; //x86 r13 register
|
|
//RegisterNeedsSib = 4; //x86 r12 register
|
|
}
|
|
|
|
// RegisterNeedsDisplacement x86 r13 register
|
|
const RegisterNeedsDisplacement = 5
|
|
|
|
// RegisterNeedsSib x86 r12 register
|
|
const RegisterNeedsSib = 4
|
|
|
|
func (sins *SuperScalarInstruction) SelectSource(cycle int, registers *[8]Register, gen *blake2.Generator) bool {
|
|
availableRegisters := make([]uint8, 0, 8)
|
|
|
|
for i := range registers {
|
|
if registers[i].Latency <= cycle {
|
|
availableRegisters = append(availableRegisters, uint8(i))
|
|
}
|
|
}
|
|
|
|
if len(availableRegisters) == 2 && sins.Opcode == S_IADD_RS {
|
|
if availableRegisters[0] == RegisterNeedsDisplacement || availableRegisters[1] == RegisterNeedsDisplacement {
|
|
sins.Src = RegisterNeedsDisplacement
|
|
sins.OpGroupPar = int(sins.Src)
|
|
return true
|
|
}
|
|
}
|
|
|
|
if selectRegister(availableRegisters, gen, &sins.Src) {
|
|
|
|
if sins.GroupParIsSource == 0 {
|
|
|
|
} else {
|
|
sins.OpGroupPar = int(sins.Src)
|
|
}
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
|
|
func (sins *SuperScalarInstruction) SelectDestination(cycle int, allowChainedMul bool, Registers *[8]Register, gen *blake2.Generator) bool {
|
|
var availableRegisters = make([]uint8, 0, 8)
|
|
|
|
for i := range Registers {
|
|
if Registers[i].Latency <= cycle && (sins.CanReuse || uint8(i) != sins.Src) &&
|
|
(allowChainedMul || sins.OpGroup != S_IMUL_R || Registers[i].LastOpGroup != S_IMUL_R) &&
|
|
(Registers[i].LastOpGroup != sins.OpGroup || Registers[i].LastOpPar != sins.OpGroupPar) &&
|
|
(sins.Opcode != S_IADD_RS || i != RegisterNeedsDisplacement) {
|
|
availableRegisters = append(availableRegisters, uint8(i))
|
|
}
|
|
}
|
|
|
|
return selectRegister(availableRegisters, gen, &sins.Dst)
|
|
}
|
|
|
|
func selectRegister(availableRegisters []uint8, gen *blake2.Generator, reg *uint8) bool {
|
|
index := 0
|
|
if len(availableRegisters) == 0 {
|
|
return false
|
|
}
|
|
|
|
if len(availableRegisters) > 1 {
|
|
tmp := gen.GetUint32()
|
|
|
|
index = int(tmp % uint32(len(availableRegisters)))
|
|
} else {
|
|
index = 0
|
|
}
|
|
*reg = availableRegisters[index]
|
|
return true
|
|
}
|
|
|
|
// executeSuperscalar execute the superscalar program
|
|
func executeSuperscalar(p []SuperScalarInstruction, r *RegisterLine) {
|
|
//TODO: produce around (14 * 8 * 8) = 896 different opcodes with hardcoded registers
|
|
|
|
for i := range p {
|
|
ins := &p[i]
|
|
switch ins.Opcode {
|
|
case S_ISUB_R:
|
|
r[ins.Dst] -= r[ins.Src]
|
|
case S_IXOR_R:
|
|
r[ins.Dst] ^= r[ins.Src]
|
|
case S_IADD_RS:
|
|
r[ins.Dst] += r[ins.Src] << ins.Imm32
|
|
case S_IMUL_R:
|
|
r[ins.Dst] *= r[ins.Src]
|
|
case S_IROR_C:
|
|
r[ins.Dst] = bits.RotateLeft64(r[ins.Dst], 0-int(ins.Imm32))
|
|
case S_IADD_C7, S_IADD_C8, S_IADD_C9:
|
|
r[ins.Dst] += signExtend2sCompl(ins.Imm32)
|
|
case S_IXOR_C7, S_IXOR_C8, S_IXOR_C9:
|
|
r[ins.Dst] ^= signExtend2sCompl(ins.Imm32)
|
|
case S_IMULH_R:
|
|
r[ins.Dst], _ = bits.Mul64(r[ins.Dst], r[ins.Src])
|
|
case S_ISMULH_R:
|
|
r[ins.Dst] = smulh(int64(r[ins.Dst]), int64(r[ins.Src]))
|
|
case S_IMUL_RCP:
|
|
r[ins.Dst] *= ins.Imm64
|
|
}
|
|
}
|
|
|
|
}
|