372 lines
11 KiB
Go
372 lines
11 KiB
Go
/*
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Copyright (c) 2019 DERO Foundation. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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package randomx
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import (
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"unsafe"
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)
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import "encoding/binary"
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//reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#51-instruction-encoding
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// VM_Instruction since go does not have union, use byte array
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type VM_Instruction [8]byte // it is hardcode 8 bytes
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func (ins VM_Instruction) IMM() uint32 {
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return binary.LittleEndian.Uint32(ins[4:])
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}
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func (ins VM_Instruction) IMM64() uint64 {
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return signExtend2sCompl(ins.IMM())
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}
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func (ins VM_Instruction) Mod() byte {
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return ins[3]
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}
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func (ins VM_Instruction) Src() byte {
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return ins[2]
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}
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func (ins VM_Instruction) Dst() byte {
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return ins[1]
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}
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func (ins VM_Instruction) Opcode() byte {
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return ins[0]
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}
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// CompileProgramToByteCode this will interpret single vm instruction into executable opcodes
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// reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#52-integer-instructions
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func CompileProgramToByteCode(prog []byte, bc *ByteCode) {
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var registerUsage [RegistersCount]int
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for i := range registerUsage {
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registerUsage[i] = -1
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}
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for i := 0; i < len(bc); i++ {
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instr := VM_Instruction(prog[i*8:])
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ibc := &bc[i]
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opcode := instr.Opcode()
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dst := instr.Dst() % RegistersCount // bit shift optimization
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src := instr.Src() % RegistersCount
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ibc.Dst = dst
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ibc.Src = src
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switch opcode {
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case 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15: // 16 frequency
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ibc.Opcode = VM_IADD_RS
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if dst != RegisterNeedsDisplacement {
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//shift
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ibc.ImmB = (instr.Mod() >> 2) % 4
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ibc.Imm = 0
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} else {
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//shift
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ibc.ImmB = (instr.Mod() >> 2) % 4
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ibc.Imm = instr.IMM64()
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}
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registerUsage[dst] = i
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case 16, 17, 18, 19, 20, 21, 22: // 7
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ibc.Opcode = VM_IADD_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_IADD_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38: // 16
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ibc.Opcode = VM_ISUB_R
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if src == dst {
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ibc.Imm = instr.IMM64()
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ibc.Opcode = VM_ISUB_I
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}
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registerUsage[dst] = i
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case 39, 40, 41, 42, 43, 44, 45: // 7
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ibc.Opcode = VM_ISUB_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_ISUB_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61: // 16
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ibc.Opcode = VM_IMUL_R
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if src == dst {
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ibc.Imm = instr.IMM64()
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ibc.Opcode = VM_IMUL_I
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}
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registerUsage[dst] = i
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case 62, 63, 64, 65: //4
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ibc.Opcode = VM_IMUL_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_IMUL_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 66, 67, 68, 69: //4
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ibc.Opcode = VM_IMULH_R
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registerUsage[dst] = i
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case 70: //1
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ibc.Opcode = VM_IMULH_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_IMULH_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 71, 72, 73, 74: //4
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ibc.Opcode = VM_ISMULH_R
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registerUsage[dst] = i
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case 75: //1
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ibc.Opcode = VM_ISMULH_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_ISMULH_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 76, 77, 78, 79, 80, 81, 82, 83: // 8
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divisor := instr.IMM()
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if !isZeroOrPowerOf2(divisor) {
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ibc.Opcode = VM_IMUL_I
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ibc.Imm = reciprocal(divisor)
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registerUsage[dst] = i
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} else {
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ibc.Opcode = VM_NOP
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}
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case 84, 85: //2
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ibc.Opcode = VM_INEG_R
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registerUsage[dst] = i
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case 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100: //15
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ibc.Opcode = VM_IXOR_R
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if src == dst {
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ibc.Imm = instr.IMM64()
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ibc.Opcode = VM_IXOR_I
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}
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registerUsage[dst] = i
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case 101, 102, 103, 104, 105: //5
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ibc.Opcode = VM_IXOR_M
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ibc.Imm = instr.IMM64()
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if src != dst {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.Opcode = VM_IXOR_MZ
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ibc.MemMask = ScratchpadL3Mask
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ibc.Imm = uint64(ibc.getScratchpadZeroAddress())
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}
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registerUsage[dst] = i
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case 106, 107, 108, 109, 110, 111, 112, 113: //8
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ibc.Opcode = VM_IROR_R
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if src == dst {
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ibc.Imm = instr.IMM64()
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ibc.Opcode = VM_IROR_I
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}
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registerUsage[dst] = i
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case 114, 115: // 2 IROL_R
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ibc.Opcode = VM_IROL_R
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if src == dst {
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ibc.Imm = instr.IMM64()
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ibc.Opcode = VM_IROL_I
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}
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registerUsage[dst] = i
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case 116, 117, 118, 119: //4
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if src != dst {
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ibc.Opcode = VM_ISWAP_R
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registerUsage[dst] = i
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registerUsage[src] = i
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} else {
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ibc.Opcode = VM_NOP
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}
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// below are floating point instructions
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case 120, 121, 122, 123: // 4
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//ibc.Opcode = VM_FSWAP_R
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if dst < RegistersCountFloat {
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ibc.Opcode = VM_FSWAP_RF
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} else {
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ibc.Opcode = VM_FSWAP_RE
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ibc.Dst = dst - RegistersCountFloat
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}
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case 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139: //16
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Src = instr.Src() % RegistersCountFloat
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ibc.Opcode = VM_FADD_R
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case 140, 141, 142, 143, 144: //5
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Opcode = VM_FADD_M
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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ibc.Imm = instr.IMM64()
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case 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160: //16
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Src = instr.Src() % RegistersCountFloat
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ibc.Opcode = VM_FSUB_R
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case 161, 162, 163, 164, 165: //5
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Opcode = VM_FSUB_M
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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ibc.Imm = instr.IMM64()
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case 166, 167, 168, 169, 170, 171: //6
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Opcode = VM_FSCAL_R
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case 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203: //32
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Src = instr.Src() % RegistersCountFloat
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ibc.Opcode = VM_FMUL_R
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case 204, 205, 206, 207: //4
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Opcode = VM_FDIV_M
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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ibc.Imm = instr.IMM64()
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case 208, 209, 210, 211, 212, 213: //6
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ibc.Dst = instr.Dst() % RegistersCountFloat // bit shift optimization
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ibc.Opcode = VM_FSQRT_R
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case 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238: //25 // CBRANCH and CFROUND are interchanged
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ibc.Opcode = VM_CBRANCH
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//TODO:??? it's +1 on other
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ibc.Dst = instr.Dst() % RegistersCount
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target := uint16(int16(registerUsage[ibc.Dst]))
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// set target!
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ibc.Src = uint8(target)
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ibc.ImmB = uint8(target >> 8)
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shift := uint64(instr.Mod()>>4) + CONDITIONOFFSET
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//conditionmask := CONDITIONMASK << shift
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ibc.Imm = instr.IMM64() | (uint64(1) << shift)
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if CONDITIONOFFSET > 0 || shift > 0 {
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ibc.Imm &= ^(uint64(1) << (shift - 1))
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}
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ibc.MemMask = CONDITIONMASK << shift
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for j := 0; j < RegistersCount; j++ {
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registerUsage[j] = i
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}
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case 239: //1
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ibc.Opcode = VM_CFROUND
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ibc.Imm = uint64(instr.IMM() & 63)
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case 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255: //16
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ibc.Opcode = VM_ISTORE
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ibc.Imm = instr.IMM64()
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if (instr.Mod() >> 4) < STOREL3CONDITION {
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if (instr.Mod() % 4) != 0 {
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ibc.MemMask = ScratchpadL1Mask
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} else {
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ibc.MemMask = ScratchpadL2Mask
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}
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} else {
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ibc.MemMask = ScratchpadL3Mask
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}
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default:
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panic("unreachable")
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}
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}
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}
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type ScratchPad [ScratchpadSize]byte
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func (pad *ScratchPad) Store64(addr uint32, val uint64) {
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*(*uint64)(unsafe.Pointer(&pad[addr])) = val
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//binary.LittleEndian.PutUint64(pad[addr:], val)
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}
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func (pad *ScratchPad) Load64(addr uint32) uint64 {
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return *(*uint64)(unsafe.Pointer(&pad[addr]))
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}
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func (pad *ScratchPad) Load32(addr uint32) uint32 {
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return *(*uint32)(unsafe.Pointer(&pad[addr]))
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}
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