206 lines
5.2 KiB
Go
206 lines
5.2 KiB
Go
package randomx
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import (
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"git.gammaspectra.live/P2Pool/go-randomx/v2/asm"
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"math"
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"math/bits"
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)
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type ByteCodeInstruction struct {
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Dst, Src byte
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ImmB uint8
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Opcode ByteCodeInstructionOp
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MemMask uint32
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Imm uint64
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/*
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union {
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int_reg_t* idst;
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rx_vec_f128* fdst;
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};
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union {
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int_reg_t* isrc;
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rx_vec_f128* fsrc;
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};
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union {
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uint64_t imm;
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int64_t simm;
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};
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InstructionType type;
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union {
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int16_t target;
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uint16_t shift;
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};
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uint32_t memMask;
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*/
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}
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func (i ByteCodeInstruction) jumpTarget() int {
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return int(int16((uint16(i.ImmB) << 8) | uint16(i.Dst)))
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}
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func (i ByteCodeInstruction) getScratchpadAddress(ptr uint64) uint32 {
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return uint32(ptr+i.Imm) & i.MemMask
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}
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func (i ByteCodeInstruction) getScratchpadZeroAddress() uint32 {
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return uint32(i.Imm) & i.MemMask
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}
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type ByteCode [RANDOMX_PROGRAM_SIZE]ByteCodeInstruction
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func (c *ByteCode) Execute(f RegisterFile, pad *ScratchPad, eMask [2]uint64) RegisterFile {
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for pc := 0; pc < RANDOMX_PROGRAM_SIZE; pc++ {
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i := &c[pc]
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switch i.Opcode {
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case VM_IADD_RS:
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f.r[i.Dst] += (f.r[i.Src] << i.ImmB) + i.Imm
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case VM_IADD_M:
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f.r[i.Dst] += pad.Load64(i.getScratchpadAddress(f.r[i.Src]))
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case VM_IADD_MZ:
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f.r[i.Dst] += pad.Load64(uint32(i.Imm))
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case VM_ISUB_R:
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f.r[i.Dst] -= f.r[i.Src]
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case VM_ISUB_I:
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f.r[i.Dst] -= i.Imm
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case VM_ISUB_M:
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f.r[i.Dst] -= pad.Load64(i.getScratchpadAddress(f.r[i.Src]))
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case VM_ISUB_MZ:
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f.r[i.Dst] -= pad.Load64(uint32(i.Imm))
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case VM_IMUL_R:
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f.r[i.Dst] *= f.r[i.Src]
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case VM_IMUL_I:
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// also handles imul_rcp
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f.r[i.Dst] *= i.Imm
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case VM_IMUL_M:
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f.r[i.Dst] *= pad.Load64(i.getScratchpadAddress(f.r[i.Src]))
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case VM_IMUL_MZ:
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f.r[i.Dst] *= pad.Load64(uint32(i.Imm))
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case VM_IMULH_R:
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f.r[i.Dst], _ = bits.Mul64(f.r[i.Dst], f.r[i.Src])
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case VM_IMULH_M:
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f.r[i.Dst], _ = bits.Mul64(f.r[i.Dst], pad.Load64(i.getScratchpadAddress(f.r[i.Src])))
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case VM_IMULH_MZ:
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f.r[i.Dst], _ = bits.Mul64(f.r[i.Dst], pad.Load64(uint32(i.Imm)))
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case VM_ISMULH_R:
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f.r[i.Dst] = smulh(int64(f.r[i.Dst]), int64(f.r[i.Src]))
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case VM_ISMULH_M:
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f.r[i.Dst] = smulh(int64(f.r[i.Dst]), int64(pad.Load64(i.getScratchpadAddress(f.r[i.Src]))))
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case VM_ISMULH_MZ:
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f.r[i.Dst] = smulh(int64(f.r[i.Dst]), int64(pad.Load64(uint32(i.Imm))))
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case VM_INEG_R:
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//f.r[i.Dst] = (^(f.r[i.Dst])) + 1 // 2's complement negative
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f.r[i.Dst] = -f.r[i.Dst]
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case VM_IXOR_R:
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f.r[i.Dst] ^= f.r[i.Src]
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case VM_IXOR_I:
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f.r[i.Dst] ^= i.Imm
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case VM_IXOR_M:
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f.r[i.Dst] ^= pad.Load64(i.getScratchpadAddress(f.r[i.Src]))
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case VM_IXOR_MZ:
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f.r[i.Dst] ^= pad.Load64(uint32(i.Imm))
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case VM_IROR_R:
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f.r[i.Dst] = bits.RotateLeft64(f.r[i.Dst], 0-int(f.r[i.Src]&63))
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case VM_IROR_I:
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//todo: can merge into VM_IROL_I
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f.r[i.Dst] = bits.RotateLeft64(f.r[i.Dst], 0-int(i.Imm&63))
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case VM_IROL_R:
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f.r[i.Dst] = bits.RotateLeft64(f.r[i.Dst], int(f.r[i.Src]&63))
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case VM_IROL_I:
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f.r[i.Dst] = bits.RotateLeft64(f.r[i.Dst], int(i.Imm&63))
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case VM_ISWAP_R:
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f.r[i.Dst], f.r[i.Src] = f.r[i.Src], f.r[i.Dst]
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case VM_FSWAP_RF:
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f.f[i.Dst][HIGH], f.f[i.Dst][LOW] = f.f[i.Dst][LOW], f.f[i.Dst][HIGH]
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case VM_FSWAP_RE:
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f.e[i.Dst][HIGH], f.e[i.Dst][LOW] = f.e[i.Dst][LOW], f.e[i.Dst][HIGH]
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case VM_FADD_R:
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f.f[i.Dst][LOW] += f.a[i.Src][LOW]
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f.f[i.Dst][HIGH] += f.a[i.Src][HIGH]
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case VM_FADD_M:
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lo, hi := pad.Load32F(i.getScratchpadAddress(f.r[i.Src]))
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f.f[i.Dst][LOW] += lo
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f.f[i.Dst][HIGH] += hi
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case VM_FSUB_R:
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f.f[i.Dst][LOW] -= f.a[i.Src][LOW]
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f.f[i.Dst][HIGH] -= f.a[i.Src][HIGH]
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case VM_FSUB_M:
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lo, hi := pad.Load32F(i.getScratchpadAddress(f.r[i.Src]))
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f.f[i.Dst][LOW] -= lo
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f.f[i.Dst][HIGH] -= hi
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case VM_FSCAL_R:
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// no dependent on rounding modes
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f.f[i.Dst][LOW] = math.Float64frombits(math.Float64bits(f.f[i.Dst][LOW]) ^ 0x80F0000000000000)
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f.f[i.Dst][HIGH] = math.Float64frombits(math.Float64bits(f.f[i.Dst][HIGH]) ^ 0x80F0000000000000)
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case VM_FMUL_R:
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f.e[i.Dst][LOW] *= f.a[i.Src][LOW]
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f.e[i.Dst][HIGH] *= f.a[i.Src][HIGH]
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case VM_FDIV_M:
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lo, hi := pad.Load32F(i.getScratchpadAddress(f.r[i.Src]))
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f.e[i.Dst][LOW] /= MaskRegisterExponentMantissa(lo, eMask[LOW])
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f.e[i.Dst][HIGH] /= MaskRegisterExponentMantissa(hi, eMask[HIGH])
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case VM_FSQRT_R:
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f.e[i.Dst][LOW] = math.Sqrt(f.e[i.Dst][LOW])
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f.e[i.Dst][HIGH] = math.Sqrt(f.e[i.Dst][HIGH])
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case VM_CBRANCH:
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f.r[i.Src] += i.Imm
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if (f.r[i.Src] & uint64(i.MemMask)) == 0 {
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pc = i.jumpTarget()
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}
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case VM_CFROUND:
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tmp := (bits.RotateLeft64(f.r[i.Src], 0-int(i.Imm))) % 4 // rotate right
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asm.SetRoundingMode(asm.RoundingMode(tmp))
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case VM_ISTORE:
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pad.Store64(i.getScratchpadAddress(f.r[i.Dst]), f.r[i.Src])
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case VM_NOP: // we do nothing
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}
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}
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return f
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}
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type ByteCodeInstructionOp int
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const (
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VM_NOP = ByteCodeInstructionOp(iota)
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VM_IADD_RS
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VM_IADD_M
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VM_IADD_MZ
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VM_ISUB_R
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VM_ISUB_I
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VM_ISUB_M
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VM_ISUB_MZ
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VM_IMUL_R
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VM_IMUL_I
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VM_IMUL_M
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VM_IMUL_MZ
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VM_IMULH_R
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VM_IMULH_M
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VM_IMULH_MZ
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VM_ISMULH_R
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VM_ISMULH_M
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VM_ISMULH_MZ
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VM_INEG_R
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VM_IXOR_R
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VM_IXOR_I
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VM_IXOR_M
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VM_IXOR_MZ
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VM_IROR_R
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VM_IROR_I
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VM_IROL_R
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VM_IROL_I
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VM_ISWAP_R
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VM_FSWAP_RF
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VM_FSWAP_RE
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VM_FADD_R
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VM_FADD_M
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VM_FSUB_R
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VM_FSUB_M
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VM_FSCAL_R
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VM_FMUL_R
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VM_FDIV_M
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VM_FSQRT_R
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VM_CBRANCH
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VM_CFROUND
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VM_ISTORE
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)
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