743 lines
20 KiB
Go
743 lines
20 KiB
Go
/*
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Copyright (c) 2019 DERO Foundation. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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package randomx
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import (
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"fmt"
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"git.gammaspectra.live/P2Pool/go-randomx/fpu"
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)
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import "math"
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import "math/bits"
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import "encoding/binary"
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//reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#51-instruction-encoding
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var Zero uint64 = 0
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// since go does not have union, use byte array
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type VM_Instruction []byte // it is hardcode 8 bytes
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func (ins VM_Instruction) IMM() uint32 {
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return binary.LittleEndian.Uint32(ins[4:])
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}
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func (ins VM_Instruction) Mod() byte {
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return ins[3]
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}
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func (ins VM_Instruction) Src() byte {
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return ins[2]
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}
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func (ins VM_Instruction) Dst() byte {
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return ins[1]
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}
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func (ins VM_Instruction) Opcode() byte {
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return ins[0]
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}
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type VM_Instruction_Type int
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const (
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VM_IADD_RS VM_Instruction_Type = 0
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VM_IADD_M VM_Instruction_Type = 1
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VM_ISUB_R VM_Instruction_Type = 2
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VM_ISUB_M VM_Instruction_Type = 3
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VM_IMUL_R VM_Instruction_Type = 4
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VM_IMUL_M VM_Instruction_Type = 5
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VM_IMULH_R VM_Instruction_Type = 6
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VM_IMULH_M VM_Instruction_Type = 7
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VM_ISMULH_R VM_Instruction_Type = 8
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VM_ISMULH_M VM_Instruction_Type = 9
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VM_IMUL_RCP VM_Instruction_Type = 10
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VM_INEG_R VM_Instruction_Type = 11
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VM_IXOR_R VM_Instruction_Type = 12
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VM_IXOR_M VM_Instruction_Type = 13
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VM_IROR_R VM_Instruction_Type = 14
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VM_IROL_R VM_Instruction_Type = 15
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VM_ISWAP_R VM_Instruction_Type = 16
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VM_FSWAP_R VM_Instruction_Type = 17
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VM_FADD_R VM_Instruction_Type = 18
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VM_FADD_M VM_Instruction_Type = 19
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VM_FSUB_R VM_Instruction_Type = 20
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VM_FSUB_M VM_Instruction_Type = 21
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VM_FSCAL_R VM_Instruction_Type = 22
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VM_FMUL_R VM_Instruction_Type = 23
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VM_FDIV_M VM_Instruction_Type = 24
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VM_FSQRT_R VM_Instruction_Type = 25
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VM_CBRANCH VM_Instruction_Type = 26
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VM_CFROUND VM_Instruction_Type = 27
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VM_ISTORE VM_Instruction_Type = 28
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VM_NOP VM_Instruction_Type = 29
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)
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var Names = map[VM_Instruction_Type]string{
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VM_IADD_RS: "VM_IADD_RS",
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VM_IADD_M: "VM_IADD_M",
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VM_ISUB_R: "VM_ISUB_R",
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VM_ISUB_M: "VM_ISUB_M",
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VM_IMUL_R: "VM_IMUL_R",
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VM_IMUL_M: "VM_IMUL_M",
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VM_IMULH_R: "VM_IMULH_R",
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VM_IMULH_M: "VM_IMULH_M",
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VM_ISMULH_R: "VM_ISMULH_R",
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VM_ISMULH_M: "VM_ISMULH_M",
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VM_IMUL_RCP: "VM_IMUL_RCP",
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VM_INEG_R: "VM_INEG_R",
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VM_IXOR_R: "VM_IXOR_R",
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VM_IXOR_M: "VM_IXOR_M",
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VM_IROR_R: "VM_IROR_R",
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VM_IROL_R: "VM_IROL_R",
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VM_ISWAP_R: "VM_ISWAP_R",
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VM_FSWAP_R: "VM_FSWAP_R",
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VM_FADD_R: "VM_FADD_R",
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VM_FADD_M: "VM_FADD_M",
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VM_FSUB_R: "VM_FSUB_R",
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VM_FSUB_M: "VM_FSUB_M",
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VM_FSCAL_R: "VM_FSCAL_R",
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VM_FMUL_R: "VM_FMUL_R",
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VM_FDIV_M: "VM_FDIV_M",
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VM_FSQRT_R: "VM_FSQRT_R",
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VM_CBRANCH: "VM_CBRANCH",
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VM_CFROUND: "VM_CFROUND",
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VM_ISTORE: "VM_ISTORE",
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VM_NOP: "VM_NOP",
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}
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// this will interpret single vm instruction
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// reference https://github.com/tevador/RandomX/blob/master/doc/specs.md#52-integer-instructions
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func (vm *VM) Compile_TO_Bytecode() {
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var registerUsage [REGISTERSCOUNT]int
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for i := range registerUsage {
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registerUsage[i] = -1
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}
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for i := 0; i < RANDOMX_PROGRAM_SIZE; i++ {
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instr := VM_Instruction(vm.Prog[i*8:])
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ibc := &vm.ByteCode[i]
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opcode := instr.Opcode()
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dst := instr.Dst() % REGISTERSCOUNT // bit shift optimization
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src := instr.Src() % REGISTERSCOUNT
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ibc.dst = dst
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ibc.src = src
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switch opcode {
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case 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15: // 16 frequency
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// ibc.Opcode = VM_NOP; break; replace opcode by nop for testing
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// fmt.Printf("VM_IADD_RS %d\n", opcode)
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ibc.Opcode = VM_IADD_RS
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ibc.idst = &vm.reg.r[dst]
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if dst != RegisterNeedsDisplacement {
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ibc.isrc = &vm.reg.r[src]
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ibc.shift = uint16((instr.Mod() >> 2) % 4)
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ibc.imm = 0
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} else {
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ibc.isrc = &vm.reg.r[src]
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ibc.shift = uint16((instr.Mod() >> 2) % 4)
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ibc.imm = signExtend2sCompl(instr.IMM())
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}
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registerUsage[dst] = i
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case 16, 17, 18, 19, 20, 21, 22: // 7
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//fmt.Printf("IADD_M opcode %d\n", opcode)
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ibc.Opcode = VM_IADD_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38: // 16
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//fmt.Printf("ISUB_R opcode %d\n", opcode)
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ibc.Opcode = VM_ISUB_R
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ibc.idst = &vm.reg.r[dst]
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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} else {
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ibc.imm = signExtend2sCompl(instr.IMM())
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ibc.isrc = &ibc.imm // we are pointing within bytecode
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}
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registerUsage[dst] = i
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case 39, 40, 41, 42, 43, 44, 45: // 7
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//fmt.Printf("ISUB_M opcode %d\n", opcode)
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ibc.Opcode = VM_ISUB_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61: // 16
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//fmt.Printf("IMUL_R opcode %d\n", opcode)
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ibc.Opcode = VM_IMUL_R
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ibc.idst = &vm.reg.r[dst]
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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} else {
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ibc.imm = signExtend2sCompl(instr.IMM())
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ibc.isrc = &ibc.imm // we are pointing within bytecode
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}
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registerUsage[dst] = i
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case 62, 63, 64, 65: //4
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//fmt.Printf("IMUL_M opcode %d\n", opcode)
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ibc.Opcode = VM_IMUL_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 66, 67, 68, 69: //4
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//fmt.Printf("IMULH_R opcode %d\n", opcode)
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ibc.Opcode = VM_IMULH_R
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ibc.idst = &vm.reg.r[dst]
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ibc.isrc = &vm.reg.r[src]
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registerUsage[dst] = i
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case 70: //1
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//fmt.Printf("IMULH_M opcode %d\n", opcode)
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ibc.Opcode = VM_IMULH_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 71, 72, 73, 74: //4
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//fmt.Printf("ISMULH_R opcode %d\n", opcode)
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ibc.Opcode = VM_ISMULH_R
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ibc.idst = &vm.reg.r[dst]
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ibc.isrc = &vm.reg.r[src]
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registerUsage[dst] = i
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case 75: //1
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//fmt.Printf("ISMULH_M opcode %d\n", opcode)
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ibc.Opcode = VM_ISMULH_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 76, 77, 78, 79, 80, 81, 82, 83: // 8
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//fmt.Printf("IMUL_RCP opcode %d\n", opcode)
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divisor := instr.IMM()
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if !isZeroOrPowerOf2(divisor) {
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ibc.Opcode = VM_IMUL_R
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = randomx_reciprocal(divisor)
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ibc.isrc = &ibc.imm
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registerUsage[dst] = i
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} else {
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ibc.Opcode = VM_NOP
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}
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case 84, 85: //2
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//fmt.Printf("INEG_R opcode %d\n", opcode)
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ibc.Opcode = VM_INEG_R
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ibc.idst = &vm.reg.r[dst]
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registerUsage[dst] = i
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case 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100: //15
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//fmt.Printf("IXOR_R opcode %d\n", opcode)
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ibc.Opcode = VM_IXOR_R
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ibc.idst = &vm.reg.r[dst]
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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} else {
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ibc.imm = signExtend2sCompl(instr.IMM())
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ibc.isrc = &ibc.imm // we are pointing within bytecode
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}
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registerUsage[dst] = i
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case 101, 102, 103, 104, 105: //5
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//fmt.Printf("IXOR_M opcode %d\n", opcode)
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ibc.Opcode = VM_IXOR_M
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ibc.idst = &vm.reg.r[dst]
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ibc.imm = signExtend2sCompl(instr.IMM())
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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if (instr.Mod() % 4) != 0 {
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ibc.memMask = ScratchpadL1Mask
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} else {
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ibc.memMask = ScratchpadL2Mask
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}
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} else {
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ibc.isrc = &Zero
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ibc.memMask = ScratchpadL3Mask
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}
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registerUsage[dst] = i
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case 106, 107, 108, 109, 110, 111, 112, 113: //8
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//fmt.Printf("IROR_R opcode %d\n", opcode)
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ibc.Opcode = VM_IROR_R
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ibc.idst = &vm.reg.r[dst]
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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} else {
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ibc.imm = signExtend2sCompl(instr.IMM())
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ibc.isrc = &ibc.imm // we are pointing within bytecode
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}
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registerUsage[dst] = i
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case 114, 115: // 2 IROL_R
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//fmt.Printf("IROL_R opcode %d\n", opcode)
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ibc.Opcode = VM_IROL_R
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ibc.idst = &vm.reg.r[dst]
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if src != dst {
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ibc.isrc = &vm.reg.r[src]
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} else {
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ibc.imm = signExtend2sCompl(instr.IMM())
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ibc.isrc = &ibc.imm // we are pointing within bytecode
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}
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registerUsage[dst] = i
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case 116, 117, 118, 119: //4
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//fmt.Printf("ISWAP_R opcode %d\n", opcode)
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if src != dst {
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ibc.Opcode = VM_ISWAP_R
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ibc.idst = &vm.reg.r[dst]
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ibc.isrc = &vm.reg.r[src]
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registerUsage[dst] = i
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registerUsage[src] = i
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} else {
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ibc.Opcode = VM_NOP
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}
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// below are floating point instructions
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case 120, 121, 122, 123: // 4
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//fmt.Printf("FSWAP_R opcode %d\n", opcode)
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ibc.Opcode = VM_FSWAP_R
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if dst < REGISTERCOUNTFLT {
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ibc.fdst = &vm.reg.f[dst]
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} else {
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ibc.fdst = &vm.reg.e[dst-REGISTERCOUNTFLT]
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}
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case 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139: //16
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//fmt.Printf("FADD_R opcode %d\n", opcode)
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dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
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src := instr.Src() % REGISTERCOUNTFLT
|
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ibc.Opcode = VM_FADD_R
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ibc.fdst = &vm.reg.f[dst]
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ibc.fsrc = &vm.reg.a[src]
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case 140, 141, 142, 143, 144: //5
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//fmt.Printf("FADD_M opcode %d\n", opcode)
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dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
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ibc.Opcode = VM_FADD_M
|
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ibc.fdst = &vm.reg.f[dst]
|
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ibc.isrc = &vm.reg.r[src]
|
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if (instr.Mod() % 4) != 0 {
|
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ibc.memMask = ScratchpadL1Mask
|
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} else {
|
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ibc.memMask = ScratchpadL2Mask
|
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}
|
|
ibc.imm = signExtend2sCompl(instr.IMM())
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|
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case 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160: //16
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//fmt.Printf("FSUB_R opcode %d\n", opcode)
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dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
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src := instr.Src() % REGISTERCOUNTFLT
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ibc.Opcode = VM_FSUB_R
|
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ibc.fdst = &vm.reg.f[dst]
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ibc.fsrc = &vm.reg.a[src]
|
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case 161, 162, 163, 164, 165: //5
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//fmt.Printf("FSUB_M opcode %d\n", opcode)
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dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
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ibc.Opcode = VM_FSUB_M
|
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ibc.fdst = &vm.reg.f[dst]
|
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ibc.isrc = &vm.reg.r[src]
|
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if (instr.Mod() % 4) != 0 {
|
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ibc.memMask = ScratchpadL1Mask
|
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} else {
|
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ibc.memMask = ScratchpadL2Mask
|
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}
|
|
ibc.imm = signExtend2sCompl(instr.IMM())
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|
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case 166, 167, 168, 169, 170, 171: //6
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|
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//fmt.Printf("FSCAL_R opcode %d\n", opcode)
|
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dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
|
ibc.Opcode = VM_FSCAL_R
|
|
ibc.fdst = &vm.reg.f[dst]
|
|
case 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203: //32
|
|
|
|
//fmt.Printf("FMUL_R opcode %d\n", opcode)
|
|
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
|
src := instr.Src() % REGISTERCOUNTFLT
|
|
ibc.Opcode = VM_FMUL_R
|
|
ibc.fdst = &vm.reg.e[dst]
|
|
ibc.fsrc = &vm.reg.a[src]
|
|
case 204, 205, 206, 207: //4
|
|
|
|
//fmt.Printf("FDIV_M opcode %d\n", opcode)
|
|
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
|
ibc.Opcode = VM_FDIV_M
|
|
ibc.fdst = &vm.reg.e[dst]
|
|
ibc.isrc = &vm.reg.r[src]
|
|
if (instr.Mod() % 4) != 0 {
|
|
ibc.memMask = ScratchpadL1Mask
|
|
} else {
|
|
ibc.memMask = ScratchpadL2Mask
|
|
}
|
|
ibc.imm = signExtend2sCompl(instr.IMM())
|
|
case 208, 209, 210, 211, 212, 213: //6
|
|
//fmt.Printf("FSQRT_R opcode %d\n", opcode)
|
|
dst := instr.Dst() % REGISTERCOUNTFLT // bit shift optimization
|
|
ibc.Opcode = VM_FSQRT_R
|
|
ibc.fdst = &vm.reg.e[dst]
|
|
|
|
case 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238: //25 // CBRANCH and CFROUND are interchanged
|
|
|
|
//fmt.Printf("CBRANCH opcode %d\n", opcode)
|
|
ibc.Opcode = VM_CBRANCH
|
|
reg := instr.Dst() % REGISTERSCOUNT
|
|
ibc.isrc = &vm.reg.r[reg]
|
|
ibc.target = int16(registerUsage[reg])
|
|
shift := uint64(instr.Mod()>>4) + CONDITIONOFFSET
|
|
//conditionmask := CONDITIONMASK << shift
|
|
ibc.imm = signExtend2sCompl(instr.IMM()) | (uint64(1) << shift)
|
|
if CONDITIONOFFSET > 0 || shift > 0 {
|
|
ibc.imm &= (^(uint64(1) << (shift - 1)))
|
|
}
|
|
ibc.memMask = CONDITIONMASK << shift
|
|
|
|
for j := 0; j < REGISTERSCOUNT; j++ {
|
|
registerUsage[j] = i
|
|
}
|
|
|
|
case 239: //1
|
|
// ibc.Opcode = VM_NOP; break; // not supported
|
|
//fmt.Printf("CFROUND opcode %d\n", opcode)
|
|
ibc.Opcode = VM_CFROUND
|
|
ibc.isrc = &vm.reg.r[src]
|
|
ibc.imm = uint64(instr.IMM() & 63)
|
|
|
|
case 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255: //16
|
|
// ibc.Opcode = VM_NOP; break;
|
|
//fmt.Printf("ISTORE opcode %d\n", opcode)
|
|
ibc.Opcode = VM_ISTORE
|
|
ibc.idst = &vm.reg.r[dst]
|
|
ibc.isrc = &vm.reg.r[src]
|
|
ibc.imm = signExtend2sCompl(instr.IMM())
|
|
if (instr.Mod() >> 4) < STOREL3CONDITION {
|
|
if (instr.Mod() % 4) != 0 {
|
|
ibc.memMask = ScratchpadL1Mask
|
|
} else {
|
|
ibc.memMask = ScratchpadL2Mask
|
|
}
|
|
|
|
} else {
|
|
ibc.memMask = ScratchpadL3Mask
|
|
}
|
|
|
|
default:
|
|
panic("unreachable")
|
|
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
type InstructionByteCode struct {
|
|
dst, src byte
|
|
idst, isrc *uint64
|
|
fdst, fsrc *[2]float64
|
|
imm uint64
|
|
simm int64
|
|
Opcode VM_Instruction_Type
|
|
target int16
|
|
shift uint16
|
|
memMask uint32
|
|
/*
|
|
union {
|
|
int_reg_t* idst;
|
|
rx_vec_f128* fdst;
|
|
};
|
|
union {
|
|
int_reg_t* isrc;
|
|
rx_vec_f128* fsrc;
|
|
};
|
|
union {
|
|
uint64_t imm;
|
|
int64_t simm;
|
|
};
|
|
InstructionType type;
|
|
union {
|
|
int16_t target;
|
|
uint16_t shift;
|
|
};
|
|
uint32_t memMask;
|
|
*/
|
|
|
|
}
|
|
|
|
func (ibc *InstructionByteCode) getScratchpadAddress() uint64 {
|
|
return (*ibc.isrc + ibc.imm) & uint64(ibc.memMask)
|
|
}
|
|
|
|
func (vm *VM) Load64(addr uint64) uint64 {
|
|
//return uint64(binary.BigEndian.Uint32(vm.ScratchPad[addr:]))| (uint64(binary.BigEndian.Uint32(vm.ScratchPad[addr+4:])) <<32)
|
|
return bits.RotateLeft64(binary.BigEndian.Uint64(vm.ScratchPad[addr:]), 32)
|
|
}
|
|
func (vm *VM) Load32(addr uint64) uint32 {
|
|
return binary.BigEndian.Uint32(vm.ScratchPad[addr:])
|
|
}
|
|
|
|
func (vm *VM) Load32F(addr uint64) float64 {
|
|
return float64(int32(vm.Load32(addr)))
|
|
}
|
|
|
|
func (vm *VM) InterpretByteCode() {
|
|
|
|
for pc := 0; pc < RANDOMX_PROGRAM_SIZE; pc++ {
|
|
|
|
ibc := &vm.ByteCode[pc]
|
|
//fmt.Printf("PCLOOP %d opcode %d %s dst %d src %d\n",pc,ibc.Opcode, Names[ibc.Opcode], ibc.dst, ibc.src)
|
|
|
|
switch ibc.Opcode {
|
|
case VM_IADD_RS:
|
|
|
|
*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm
|
|
|
|
//panic("VM_IADD_RS")
|
|
case VM_IADD_M:
|
|
*ibc.idst += vm.Load64(ibc.getScratchpadAddress())
|
|
|
|
//panic("VM_IADD_M")
|
|
case VM_ISUB_R:
|
|
*ibc.idst -= *ibc.isrc
|
|
|
|
//panic("VM_ISUB_R")
|
|
|
|
case VM_ISUB_M:
|
|
|
|
*ibc.idst -= vm.Load64(ibc.getScratchpadAddress())
|
|
|
|
//panic("VM_ISUB_M")
|
|
case VM_IMUL_R: // also handles imul_rcp
|
|
|
|
*ibc.idst *= *ibc.isrc
|
|
|
|
//panic("VM_IMUL_R")
|
|
case VM_IMUL_M:
|
|
*ibc.idst *= vm.Load64(ibc.getScratchpadAddress())
|
|
|
|
//panic("VM_IMUL_M")
|
|
case VM_IMULH_R:
|
|
|
|
*ibc.idst, _ = bits.Mul64(*ibc.idst, *ibc.isrc)
|
|
|
|
// panic("VM_IMULH_R")
|
|
case VM_IMULH_M:
|
|
*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadAddress()))
|
|
// fmt.Printf("%x \n",*ibc.idst )
|
|
// panic("VM_IMULH_M")
|
|
case VM_ISMULH_R:
|
|
*ibc.idst = uint64(smulh(int64(*ibc.idst), int64(*ibc.isrc)))
|
|
// fmt.Printf("dst %x\n", *ibc.idst)
|
|
// panic("VM_ISMULH_R")
|
|
case VM_ISMULH_M:
|
|
*ibc.idst = uint64(smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadAddress()))))
|
|
//fmt.Printf("%x \n",*ibc.idst )
|
|
// panic("VM_ISMULH_M")
|
|
case VM_INEG_R:
|
|
*ibc.idst = (^(*ibc.idst)) + 1 // 2's complement negative
|
|
|
|
//panic("VM_INEG_R")
|
|
case VM_IXOR_R:
|
|
*ibc.idst ^= *ibc.isrc
|
|
|
|
case VM_IXOR_M:
|
|
*ibc.idst ^= vm.Load64(ibc.getScratchpadAddress())
|
|
|
|
//panic("VM_IXOR_M")
|
|
case VM_IROR_R:
|
|
*ibc.idst = bits.RotateLeft64(*ibc.idst, 0-int(*ibc.isrc&63))
|
|
|
|
//panic("VM_IROR_R")
|
|
|
|
case VM_IROL_R:
|
|
*ibc.idst = bits.RotateLeft64(*ibc.idst, int(*ibc.isrc&63))
|
|
|
|
case VM_ISWAP_R:
|
|
*ibc.idst, *ibc.isrc = *ibc.isrc, *ibc.idst
|
|
//fmt.Printf("%x %x\n",*ibc.idst, *ibc.isrc )
|
|
//panic("VM_ISWAP_R")
|
|
case VM_FSWAP_R:
|
|
//TODO: could be F+E
|
|
|
|
ibc.fdst[HIGH], ibc.fdst[LOW] = ibc.fdst[LOW], ibc.fdst[HIGH]
|
|
// fmt.Printf("%+v \n",ibc.fdst )
|
|
// panic("VM_FSWAP_R")
|
|
case VM_FADD_R:
|
|
ibc.fdst[LOW] += ibc.fsrc[LOW]
|
|
ibc.fdst[HIGH] += ibc.fsrc[HIGH]
|
|
|
|
//panic("VM_FADD_R")
|
|
case VM_FADD_M:
|
|
ibc.fdst[LOW] += vm.Load32F(ibc.getScratchpadAddress() + 0)
|
|
ibc.fdst[HIGH] += vm.Load32F(ibc.getScratchpadAddress() + 4)
|
|
|
|
//panic("VM_FADD_M")
|
|
case VM_FSUB_R:
|
|
ibc.fdst[LOW] -= ibc.fsrc[LOW]
|
|
ibc.fdst[HIGH] -= ibc.fsrc[HIGH]
|
|
|
|
//fmt.Printf("fdst float %+v\n", ibc.fdst )
|
|
//panic("VM_FSUB_R")
|
|
case VM_FSUB_M:
|
|
ibc.fdst[LOW] -= vm.Load32F(ibc.getScratchpadAddress() + 0)
|
|
ibc.fdst[HIGH] -= vm.Load32F(ibc.getScratchpadAddress() + 4)
|
|
|
|
//panic("VM_FSUB_M")
|
|
case VM_FSCAL_R: // no dependent on rounding modes
|
|
//mask := math.Float64frombits(0x80F0000000000000)
|
|
ibc.fdst[LOW] = math.Float64frombits(math.Float64bits(ibc.fdst[LOW]) ^ 0x80F0000000000000)
|
|
ibc.fdst[HIGH] = math.Float64frombits(math.Float64bits(ibc.fdst[HIGH]) ^ 0x80F0000000000000)
|
|
|
|
//fmt.Printf("fdst float %+v\n", ibc.fdst )
|
|
//panic("VM_FSCA_M")
|
|
case VM_FMUL_R:
|
|
ibc.fdst[LOW] *= ibc.fsrc[LOW]
|
|
ibc.fdst[HIGH] *= ibc.fsrc[HIGH]
|
|
|
|
//panic("VM_FMUL_R")
|
|
case VM_FDIV_M:
|
|
ibc.fdst[LOW] /= MaskRegisterExponentMantissa(vm.Load32F(ibc.getScratchpadAddress()+0), vm.config.eMask[LOW])
|
|
ibc.fdst[HIGH] /= MaskRegisterExponentMantissa(vm.Load32F(ibc.getScratchpadAddress()+4), vm.config.eMask[HIGH])
|
|
|
|
//panic("VM_FDIV_M")
|
|
case VM_FSQRT_R:
|
|
ibc.fdst[LOW] = math.Sqrt(ibc.fdst[LOW])
|
|
ibc.fdst[HIGH] = math.Sqrt(ibc.fdst[HIGH])
|
|
|
|
// panic("VM_FSQRT")
|
|
case VM_CBRANCH:
|
|
//fmt.Printf("pc %d src %x imm %x\n",pc ,*ibc.isrc, ibc.imm)
|
|
*ibc.isrc += ibc.imm
|
|
//fmt.Printf("pc %d\n",pc)
|
|
if (*ibc.isrc & uint64(ibc.memMask)) == 0 {
|
|
pc = int(ibc.target)
|
|
|
|
}
|
|
|
|
// fmt.Printf("pc %d\n",pc)
|
|
//panic("VM_CBRANCH")
|
|
case VM_CFROUND:
|
|
|
|
tmp := (bits.RotateLeft64(*ibc.isrc, 0-int(ibc.imm))) % 4 // rotate right
|
|
fpu.SetRoundingMode(fpu.RoundingMode(tmp))
|
|
|
|
//panic("round not implemented")
|
|
//panic("VM_CFROUND")
|
|
case VM_ISTORE:
|
|
binary.BigEndian.PutUint64(vm.ScratchPad[(*ibc.idst+ibc.imm)&uint64(ibc.memMask):], bits.RotateLeft64(*ibc.isrc, 32))
|
|
|
|
//panic("VM_ISTOREM")
|
|
|
|
case VM_NOP: // we do nothing
|
|
|
|
default:
|
|
panic("instruction not implemented")
|
|
|
|
}
|
|
/*fmt.Printf("REGS ")
|
|
for j := 0; j <7;j++ {
|
|
fmt.Printf("%16x, " , vm.reg.r[j])
|
|
}
|
|
fmt.Printf("\n")
|
|
*/
|
|
|
|
}
|
|
}
|
|
|
|
var umm888_ = fmt.Sprintf("")
|