238 lines
8.1 KiB
C
Executable File
238 lines
8.1 KiB
C
Executable File
/**************************************************************************
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Copyright (c) 2006-2013, Silicom
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Silicom nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#ifndef BYPASS_H
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#define BYPASS_H
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/* Bypass related */
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#define SYNC_CMD_VAL 2 /* 10b */
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#define SYNC_CMD_LEN 2
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#define WR_CMD_VAL 2 /* 10b */
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#define WR_CMD_LEN 2
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#define RD_CMD_VAL 1 /* 10b */
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#define RD_CMD_LEN 2
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#define ADDR_CMD_LEN 4
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#define WR_DATA_LEN 8
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#define RD_DATA_LEN 8
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#define PIC_SIGN_REG_ADDR 0x7
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#define PIC_SIGN_VALUE 0xcd
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#define STATUS_REG_ADDR 0
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#define WDT_EN_MASK 0x01 //BIT_0
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#define CMND_EN_MASK 0x02 //BIT_1
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#define DIS_BYPASS_CAP_MASK 0x04 //BIT_2 /* Bypass Cap is disable*/
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#define DFLT_PWRON_MASK 0x08 //BIT_3
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#define BYPASS_OFF_MASK 0x10 //BIT_4
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#define BYPASS_FLAG_MASK 0x20 //BIT_5
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#define STD_NIC_MASK (DIS_BYPASS_CAP_MASK | BYPASS_OFF_MASK | DFLT_PWRON_MASK)
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#define WD_EXP_FLAG_MASK 0x40 //BIT_6
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#define DFLT_PWROFF_MASK 0x80 //BIT_7
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#define STD_NIC_PWOFF_MASK (DIS_BYPASS_CAP_MASK | BYPASS_OFF_MASK | DFLT_PWRON_MASK | DFLT_PWROFF_MASK)
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#define PRODUCT_CAP_REG_ADDR 0x5
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#define BYPASS_SUPPORT_MASK 0x01 //BIT_0
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#define TAP_SUPPORT_MASK 0x02 //BIT_1
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#define NORMAL_UNSUPPORT_MASK 0x04 /*BIT_2*/
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#define DISC_SUPPORT_MASK 0x08 //BIT_3
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#define TPL2_SUPPORT_MASK 0x10 //BIT_4
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#define DISC_PORT_SUPPORT_MASK 0x20 //BIT_5
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#define STATUS_TAP_REG_ADDR 0x6
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#define WDTE_TAP_BPN_MASK 0x01 //BIT_1 /* 1 when wdt expired -> TAP, 0 - Bypass */
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#define DIS_TAP_CAP_MASK 0x04 //BIT_2 /* TAP Cap is disable*/
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#define DFLT_PWRON_TAP_MASK 0x08 //BIT_3
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#define TAP_OFF_MASK 0x10 //BIT_4
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#define TAP_FLAG_MASK 0x20 //BIT_5
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#define TX_DISA_MASK 0x40
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#define TX_DISB_MASK 0x80
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#define STD_NIC_TAP_MASK (DIS_TAP_CAP_MASK | TAP_OFF_MASK | DFLT_PWRON_TAP_MASK)
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#define STATUS_DISC_REG_ADDR 13
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#define WDTE_DISC_BPN_MASK 0x01 //BIT_0 /* 1 when wdt expired -> TAP, 0 - Bypass */
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#define STD_NIC_ON_MASK 0x02 //BIT_1
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#define DIS_DISC_CAP_MASK 0x04 //BIT_2 /* TAP Cap is disable*/
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#define DFLT_PWRON_DISC_MASK 0x08 //BIT_3
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#define DISC_OFF_MASK 0x10 //BIT_4
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#define DISC_FLAG_MASK 0x20 //BIT_5
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#define TPL2_FLAG_MASK 0x40 //BIT_6
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#define STD_NIC_DISC_MASK DIS_DISC_CAP_MASK
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#define CONT_CONFIG_REG_ADDR 12
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#define EN_HW_RESET_MASK 0x2 /* BIT_1 */
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#define WAIT_AT_PWUP_MASK 0x1 /* BIT_0 */
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#define VER_REG_ADDR 0x1
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#define BP_FW_VER_A0 0xa0
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#define BP_FW_VER_A1 0xa1
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#define INT_VER_MASK 0xf0
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#define EXT_VER_MASK 0xf
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/* */
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#define PXG2BPI_VER 0x0
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#define PXG2TBPI_VER 0x1
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#define PXE2TBPI_VER 0x2
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#define PXG4BPFI_VER 0x4
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#define BP_FW_EXT_VER7 0x6
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#define BP_FW_EXT_VER8 0x8
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#define BP_FW_EXT_VER9 0x9
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#define OLD_IF_VER -1
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#define CMND_REG_ADDR 10 /* 1010b */
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#define WDT_REG_ADDR 4
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#define TMRL_REG_ADDR 2
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#define TMRH_REG_ADDR 3
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/* NEW_FW */
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#define WDT_INTERVAL 5 //20
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#define WDT_CMND_INTERVAL 200 //50
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#define CMND_INTERVAL 200 //100 /* usec */
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#define PULSE_TIME 100
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/* OLD_FW */
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#define INIT_CMND_INTERVAL 40
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#define PULSE_INTERVAL 5
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#define WDT_TIME_CNT 3
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/* Intel Commands */
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#define CMND_OFF_INT 0xf
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#define PWROFF_BYPASS_ON_INT 0x5
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#define BYPASS_ON_INT 0x6
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#define DIS_BYPASS_CAP_INT 0x4
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#define RESET_WDT_INT 0x1
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/* Intel timing */
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#define BYPASS_DELAY_INT 4 /* msec */
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#define CMND_INTERVAL_INT 2 /* msec */
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/* Silicom Commands */
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#define CMND_ON 0x4
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#define CMND_OFF 0x2
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#define BYPASS_ON 0xa
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#define BYPASS_OFF 0x8
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#define PORT_LINK_EN 0xe
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#define PORT_LINK_DIS 0xc
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#define WDT_ON 0x10 /* 0x1f (11111) - max*/
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#define TIMEOUT_UNIT 100
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#define TIMEOUT_MAX_STEP 15
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#define WDT_TIMEOUT_MIN 100 /* msec */
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#define WDT_TIMEOUT_MAX 3276800 /* msec */
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#define WDT_AUTO_MIN_INT 500
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#define WDT_TIMEOUT_DEF WDT_TIMEOUT_MIN
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#define WDT_OFF 0x6
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#define WDT_RELOAD 0x9
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#define RESET_CONT 0x20
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#define DIS_BYPASS_CAP 0x22
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#define EN_BYPASS_CAP 0x24
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#define BYPASS_STATE_PWRON 0x26
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#define NORMAL_STATE_PWRON 0x28
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#define BYPASS_STATE_PWROFF 0x27
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#define NORMAL_STATE_PWROFF 0x29
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#define TAP_ON 0xb
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#define TAP_OFF 0x9
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#define TAP_STATE_PWRON 0x2a
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#define DIS_TAP_CAP 0x2c
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#define EN_TAP_CAP 0x2e
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#define STD_NIC_OFF 0x86
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#define STD_NIC_ON 0x84
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#define DISC_ON 0x85
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#define DISC_OFF 0x8a
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#define DISC_STATE_PWRON 0x87
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#define DIS_DISC_CAP 0x88
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#define EN_DISC_CAP 0x89
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#define TPL2_ON 0x8c
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#define TPL2_OFF 0x8b
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#define BP_WAIT_AT_PWUP_EN 0x80
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#define BP_WAIT_AT_PWUP_DIS 0x81
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#define BP_HW_RESET_EN 0x82
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#define BP_HW_RESET_DIS 0x83
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#define TX_DISA 0x8d
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#define TX_DISB 0x8e
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#define TX_ENA 0xA0
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#define TX_ENB 0xA1
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#define TX_DISA_PWRUP 0xA2
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#define TX_DISB_PWRUP 0xA3
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#define TX_ENA_PWRUP 0xA4
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#define TX_ENB_PWRUP 0xA5
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#define BYPASS_CAP_DELAY 35 /* msec */
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#define DFLT_PWRON_DELAY 10 /* msec */
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#define LATCH_DELAY 15 /* msec */
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#define EEPROM_WR_DELAY 20 /* msec */
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#define BP_LINK_MON_DELAY 4 /* sec */
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#define BP_FW_EXT_VER0 0xa0
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#define BP_FW_EXT_VER1 0xa1
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#define BP_FW_EXT_VER2 0xb1
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#define BP_OK 0
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#define BP_NOT_CAP -1
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#define WDT_STATUS_EXP -2
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#define WDT_STATUS_UNKNOWN -1
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#define WDT_STATUS_EN 1
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#define WDT_STATUS_DIS 0
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#define ETH_P_BPTEST 0xabba
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#define BPTEST_DATA_LEN 60
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#endif /* BYPASS_H*/
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