Added further documentation from datasheet, fixed typos
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84
src/pcie.asm
84
src/pcie.asm
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@ -116,6 +116,35 @@ lock_PCIE_SBUS_release:
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RET
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; FASTCALL bool, uint result(uint & 0xff Register, uint & 0xff DeviceAddress, bool doRead, uint commandData). bool is in RRET, result in RRET_X
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;
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; This is defined on datasheet, page 372, 9.3 SerDes Management and Temperature as pseudocode:
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;
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; sbus_xxx_command (device, register, command, data)
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; {
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; // Write data
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; SBUS_XXX_REQUEST = data;
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; // Start command
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; SBUS_XXX_COMMAND = (1 << 24) /*Execute*/
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; + (((command==Write) ? 0x21 : (command==Read) ? 0x22 : 0x0) << 16)
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; + (device << 8)
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; + (register);
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;
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; // Wait for command to complete
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; while (SBUS_XXX_COMMAND.Busy) yield();
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;
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; // Check result status (optional; failure indicates invalid device number)
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; result = SBUS_XXX_COMMAND.ResultCode;
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; if ( command == Write && result != 0x1 ) error;
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; if ( command == Read && result != 0x4 ) error;
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;
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; // Clear register for next command
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; SBUS_XXX_COMMAND = 0;
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;
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; // Read data
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; data = SBUS_XXX_RESPONSE;
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; return data;
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; }
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;
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execute_SBus_PCIE_Command:
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MOV~03 SBUS_PCIE_REQUEST, P3 ; Set commandData into the request
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SHL R0, P1, 8 ; P1 << 8
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@ -154,32 +183,38 @@ init_PCIE_MASTER_SPICO:
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MOV api_PCIE_MASTER_STATUS, 0
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MOV api_BSM_STATUS, 0x0101000e
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FASTCALL @execute_SBus_PCIE_Command, 0x0a, 0xfe, 0, 0x01
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; Set SBus frequency to refclk/2 for ethernet
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FASTCALL @execute_SBus_PCIE_Command, 0x0a, platform_PCIE_SBUS_CONTROLLER_DEVICE_ADDRESS, 0, 0x01
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Place Master SPICO into Reset and Enable off
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0xc0
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Remove Reset, Enable off, IMEM_CNTL_EN on
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x0240
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Set starting IMEM address for burst download
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FASTCALL @execute_SBus_PCIE_Command, 0x03, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x80000000
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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MOV api_BSM_STATUS, 0x0102000e
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; Write firmware image to Master SPICO
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CALL @download_master_spico_fw
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MOV api_BSM_STATUS, 0x0103000e
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x40
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; Start the Master SPICO controller
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x40 ; Set IMEM_CNTL_EN off
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x16, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x000c0000
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FASTCALL @execute_SBus_PCIE_Command, 0x16, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x000c0000 ; Turn ECC on
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x0140
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FASTCALL @execute_SBus_PCIE_Command, 0x01, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x0140 ; Set SPICO_ENABLE on
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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MOV api_MASTER_FW_VERSION, plaftorm_MASTER_FW_VERSION
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MOV api_MASTER_FW_VERSION, platform_MASTER_FW_VERSION
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MOV RRET, 1 ; Success
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MOV api_BSM_STATUS, 0x0108000e
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@ -198,15 +233,17 @@ init_ALL_PCIE_SERDES_SPICO:
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MOV R0, 0 ; Why, this must be a constant!
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BEQ R0, 1, 0x1, @.skipUnlock
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MOV api_BSM_STATUS, 0x0001000e
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MOV api_BSM_STATUS, 0x0001000e
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; Place SerDes in Reset & disable SPICO
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FASTCALL @execute_SBus_PCIE_Command, 0x07, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x11
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Remove SerDes Reset
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FASTCALL @execute_SBus_PCIE_Command, 0x07, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x10
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Assert IMEM override
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FASTCALL @execute_SBus_PCIE_Command, 0x00, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x40000000
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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@ -231,32 +268,36 @@ init_ALL_PCIE_SERDES_SPICO:
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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.skipLock: ; (??)
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FASTCALL @execute_SBus_PCIE_Command, 0x00, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x00
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; Start SerDes controller
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FASTCALL @execute_SBus_PCIE_Command, 0x00, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x00 ; IMEM override off
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x0b, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x0c0000
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FASTCALL @execute_SBus_PCIE_Command, 0x0b, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x0c0000 ; Turn ECC on
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x07, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x02
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FASTCALL @execute_SBus_PCIE_Command, 0x07, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x02 ; Turn SPICO Enable on
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x08, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x00
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FASTCALL @execute_SBus_PCIE_Command, 0x08, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x00 ; Enable core and hardware interrupts
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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.skipFullLock: ; (??)
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MOV api_SERDES_FW_VERSION, plaftorm_SERDES_FW_VERSION
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MOV api_SERDES_FW_VERSION, platform_SERDES_FW_VERSION
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; TODO: move this to its own call
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MOV R3, 1 ; Why, this must be a constant!. Also registered loc_089110_load_config_unknown_1 on original code
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BEQ R3, 0, 0x1, @.successCommand ; Skip CRC and version checks
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MOV api_BSM_STATUS, 0x0004000e
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; Execute Master SPICO CRC check interrupt
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FASTCALL @execute_SBus_PCIE_Command, 0x02, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x02 ; Do MASTER FW CRC check
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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FASTCALL @execute_SBus_PCIE_Command, 0x07, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x01 ; Do MASTER FW CRC check read result
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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; Execute SerDes CRC check interrupts (broadcast)
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FASTCALL @execute_SBus_PCIE_Command, 0x03, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x3c0000 ; Do All SerDes FW CRC check
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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@ -265,9 +306,10 @@ init_ALL_PCIE_SERDES_SPICO:
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.doMasterCRCCheck:
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FASTCALL @execute_SBus_PCIE_Command, 0x09, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 1, 0x00 ; Check MASTER FW CRC check
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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BEQ RRET_X, 0x00008000, 0x00008000, @.doMasterCRCCheck ; If not finish check yet?
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BEQ RRET_X, 0x00008000, 0x00008000, @.doMasterCRCCheck ; Poll Master SPICO for completion (only check bit[15])
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BNE RRET_X, 0x00010000, 0xffff0000, @.doAllSerdesCRCCheck ; If check failed, skip setting the proper value
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; Check Master SPICO result
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BNE RRET_X, 0x00010000, 0xffff0000, @.doAllSerdesCRCCheck ; If check failed, skip setting the proper value, (0x0001 is pass, 0xFFFF is fail)
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; Command Executed
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SET api_BSM_STATUS, 0x00100000, 0x00100000 ; Set Master CRC = OK
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MOV api_PCIE_FW_CHECK_STATUS, api_BSM_STATUS
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@ -283,9 +325,10 @@ init_ALL_PCIE_SERDES_SPICO:
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.doSingleSerdesCRCCheck:
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FASTCALL @execute_SBus_PCIE_Command, 0x04, BSM_COUNTER_1, 1, 0x00 ; Do SerDes SPICO read
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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BEQ RRET_X, 0x00010000, 0x00010000, @.doSingleSerdesCRCCheck ; If not finish check yet?
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BEQ RRET_X, 0x00010000, 0x00010000, @.doSingleSerdesCRCCheck ; Poll SerDes for completion (only check bit[16])
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BNE RRET_X, 0x00000000, 0x0000ffff, @.finishAllSerdesCRCCheck ; If check failed, skip setting the proper value
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; Check SerDes result
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BNE RRET_X, 0x00000000, 0x0000ffff, @.finishAllSerdesCRCCheck ; If check failed, skip setting the proper value, (0x00 is pass, 0xFF is fail)
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; Prepare and set register for success
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MOV R4, 0x00000001
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BEQ BSM_COUNTER_1, platform_SERDES_SPICO_COUNT, 0xffffffff, @.setAllSerdesCRCCheckValue ; Number of SerDes SPICO
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@ -307,6 +350,7 @@ init_ALL_PCIE_SERDES_SPICO:
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MOV api_PCIE_FW_CHECK_STATUS, api_BSM_STATUS
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.doMasterVersionCheck:
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; Execute Master SPICO Revision check interrupt
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FASTCALL @execute_SBus_PCIE_Command, 0x02, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 0, 0x00 ; Do MASTER FW Version check
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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@ -316,7 +360,7 @@ init_ALL_PCIE_SERDES_SPICO:
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.doMasterVersionCheckRead:
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FASTCALL @execute_SBus_PCIE_Command, 0x08, platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS, 1, 0x00 ; Check MASTER FW Version
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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BEQ RRET_X, 0x00008000, 0x00008000, @.doMasterVersionCheckRead ; If not finish check yet?
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BEQ RRET_X, 0x00008000, 0x00008000, @.doMasterVersionCheckRead ; Poll Master SPICO for completion (only check bit[15])
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; Compare api_MASTER_FW_VERSION and Returned version
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AND R6, api_MASTER_FW_VERSION, 0xffff0000
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@ -329,7 +373,7 @@ init_ALL_PCIE_SERDES_SPICO:
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MOV api_PCIE_FW_CHECK_STATUS, api_BSM_STATUS
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.doAllSerdesVersionCheck:
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; Execute SerDes Revision check interrupts (broadcast)
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FASTCALL @execute_SBus_PCIE_Command, 0x03, platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS, 0, 0x00 ; Do All SerDes FW Version check
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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WRITE api_SERDES_STATUS_3, 0x00000000, 0x00000000 ; 64-bit write
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@ -347,7 +391,7 @@ init_ALL_PCIE_SERDES_SPICO:
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.doSingleSerdesVersionCheck:
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FASTCALL @execute_SBus_PCIE_Command, 0x04, BSM_COUNTER_1, 1, 0x00 ; Do SerDes SPICO read
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BNE RRET, 1, 0x1, @.failCommand ; Command failed
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BEQ RRET_X, 0x00010000, 0x00010000, @.doSingleSerdesVersionCheck ; If not finish check yet?
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BEQ RRET_X, 0x00010000, 0x00010000, @.doSingleSerdesVersionCheck ; Poll SerDes for completion (only check bit[16])
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AND R7, RRET_X, 0x0000ffff
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SUB R7, R6, R7 ; Compare against api_SERDES_FW_VERSION
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@ -421,7 +465,7 @@ init_PCIE_EACH_SERDES_SPICO:
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.continue:
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BNE R0, platform_SERDES_SPICO_COUNT, 0xFFFFFFFF, @.do
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MOV R0, 3 ; Current SERDES device index, odd
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MOV R0, 3 ; Current SERDES device index, odd, for PCS access
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MOV R1, 0x000000d0 ; Current data to write
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.do2:
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FASTCALL @execute_SBus_PCIE_Command, 0x24, R0, 0, R1 ; Execute command
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@ -30,10 +30,16 @@
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.constant platform_PCIE_SBUS_LOCK_NVM 1
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.constant platform_PCIE_SBUS_LOCK_API 2
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.constant platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS 0xfd
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.constant platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS 0xff
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.constant platform_SERDES_SPICO_COUNT 0x42
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.constant platform_PCIE_RMON0_DEVICE_ADDRESS 1
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; Here go PCIe Lane 0-66 even 0xFF bcast, and PCIe lane PCS 3-67 odd 0xF7 bcast
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.constant platform_PCIE_RMON1_DEVICE_ADDRESS 68
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.constant platform_PCIE_THERMAL_SENSE_DEVICE_ADDRESS 69
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.constant platform_PCIE_PMRO_DEVICE_ADDRESS 70
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.constant platform_PCIE_MASTER_SPICO_DEVICE_ADDRESS 0xfd
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.constant platform_PCIE_SBUS_CONTROLLER_DEVICE_ADDRESS 0xfe
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.constant platform_PCIE_ALL_SERDES_SPICO_DEVICE_ADDRESS 0xff
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; Change this?
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.constant platform_PCIE_SBUS_LOCK_HOLD BSM_SCRATCH_START +0x166
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