FM10K/rrcc
FM10K/rrcc
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base: FM10K:d03db39486084ce4a5ff67e21b721d138f71027e
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FM10K:master
FM10K:v0.3.0
FM10K:v0.2.0
FM10K:v0.1.0
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compare: FM10K:9e9a6a93a2077f0d13b48f213d9427ecdd78584a
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FM10K:master
FM10K:v0.3.0
FM10K:v0.2.0
FM10K:v0.1.0

3 commits
d03db39486 ... 9e9a6a93a2

Author SHA1 Message Date
DataHoarder 9e9a6a93a2 Added PCIE/INTERRUPT bitfields
Some checks reported errors
continuous-integration/drone/push Build was killed
Details
2021-08-03 23:08:56 +02:00
DataHoarder 86f808291b Extended SET to include virtual dynamic way of setting bits on offset/register cases 2021-08-03 22:20:59 +02:00
DataHoarder ec5421ff3c Add third offset parseOperatorResult 2021-08-03 22:14:19 +02:00
3 changed files with 184 additions and 25 deletions
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146
asm/registers.asm
View file

@ -33,9 +33,9 @@
.constant DEVICE_CFG, %0x4
.bitfield DEVICE_CFG.PCIeMode 0, 4
.bitfield DEVICE_CFG.PCIeMode_0 0
.bitfield DEVICE_CFG.PCIeMode_1 1
.bitfield DEVICE_CFG.PCIeMode_2 2
.bitfield DEVICE_CFG.PCIeMode_3 3
.bitfield DEVICE_CFG.PCIeMode_2 1
.bitfield DEVICE_CFG.PCIeMode_4 2
.bitfield DEVICE_CFG.PCIeMode_6 3
.bitfield DEVICE_CFG.Eth100GDisabled 4
.bitfield DEVICE_CFG.FeatureCode 5, 2
.bitfield DEVICE_CFG.PCIeEnable 7, 9
@ -57,11 +57,13 @@
.constant MGMT_SCRATCH_1, MGMT_SCRATCH_0 +1
.constant VITAL_PRODUCT_DATA, %0x304
.bitfield VITAL_PRODUCT_DATA.PartNumber 0, 16
;; These are the interrupts detect/mask that exist. All use same bitfields
.constant GLOBAL_INTERRUPT_DETECT_0, %0x400
.constant GLOBAL_INTERRUPT_DETECT_1, %0x401
.constant INTERRUPT_MASK_INT, %0x402
.constant INTERRUPT_MASK_INT_0, %0x402
.constant INTERRUPT_MASK_INT_1, %0x403
.constant INTERRUPT_MASK_PCIE_0, %0x420
.constant INTERRUPT_MASK_PCIE_1, %0x422
.constant INTERRUPT_MASK_PCIE_2, %0x424
@ -71,13 +73,64 @@
.constant INTERRUPT_MASK_PCIE_6, %0x42c
.constant INTERRUPT_MASK_PCIE_7, %0x42e
.constant INTERRUPT_MASK_PCIE_8, %0x431
.constant INTERRUPT_MASK_FIBM_0, %0x440
.constant INTERRUPT_MASK_FIBM_1, %0x441
.constant INTERRUPT_MASK_BSM_0, %0x442
.constant INTERRUPT_MASK_BSM_1, %0x443
.bitfield INTERRUPTS_0.PCIE_BSM 0, 9
.bitfield INTERRUPTS_0.PCIE_BSM_0 0
.bitfield INTERRUPTS_0.PCIE_BSM_1 1
.bitfield INTERRUPTS_0.PCIE_BSM_2 2
.bitfield INTERRUPTS_0.PCIE_BSM_3 3
.bitfield INTERRUPTS_0.PCIE_BSM_4 4
.bitfield INTERRUPTS_0.PCIE_BSM_5 5
.bitfield INTERRUPTS_0.PCIE_BSM_6 6
.bitfield INTERRUPTS_0.PCIE_BSM_7 7
.bitfield INTERRUPTS_0.PCIE_BSM_8 8
.bitfield INTERRUPTS_0.PCIE 9, 9
.bitfield INTERRUPTS_0.PCIE_0 9
.bitfield INTERRUPTS_0.PCIE_1 10
.bitfield INTERRUPTS_0.PCIE_2 11
.bitfield INTERRUPTS_0.PCIE_3 12
.bitfield INTERRUPTS_0.PCIE_4 13
.bitfield INTERRUPTS_0.PCIE_5 14
.bitfield INTERRUPTS_0.PCIE_6 15
.bitfield INTERRUPTS_0.PCIE_7 16
.bitfield INTERRUPTS_0.PCIE_8 17
.bitfield INTERRUPTS_0.EPL 18, 9
.bitfield INTERRUPTS_0.EPL_0 18
.bitfield INTERRUPTS_0.EPL_1 19
.bitfield INTERRUPTS_0.EPL_2 20
.bitfield INTERRUPTS_0.EPL_3 21
.bitfield INTERRUPTS_0.EPL_4 22
.bitfield INTERRUPTS_0.EPL_5 23
.bitfield INTERRUPTS_0.EPL_6 24
.bitfield INTERRUPTS_0.EPL_7 25
.bitfield INTERRUPTS_0.EPL_8 26
.bitfield INTERRUPTS_0.TUNNEL 27, 2
.bitfield INTERRUPTS_0.TUNNEL_0 27
.bitfield INTERRUPTS_0.TUNNEL_1 28
.bitfield INTERRUPTS_0.CORE, 29
.bitfield INTERRUPTS_0.SOFTWARE, 30
.bitfield INTERRUPTS_0.GPIO, 31
.bitfield INTERRUPTS_1.I2C, 0
.bitfield INTERRUPTS_1.MDIO, 1
.bitfield INTERRUPTS_1.CRM, 2
.bitfield INTERRUPTS_1.FH_TAIL, 3
.bitfield INTERRUPTS_1.FH_HEAD, 4
.bitfield INTERRUPTS_1.SBUS_EPL, 5
.bitfield INTERRUPTS_1.SBUS_PCIE, 6
.bitfield INTERRUPTS_1.PINS, 7
.bitfield INTERRUPTS_1.FIBM, 8
.bitfield INTERRUPTS_1.BSM, 9
.bitfield INTERRUPTS_1.XCLK, 10
.constant CORE_INTERRUPT_DETECT, %0x444
.constant CORE_INTERRUPT_MASK, %0x445
.constant SRAM_ERR_IP_0, %0x446
.constant SRAM_ERR_IP_1, %0x447
.constant SRAM_ERR_IM_0, %0x448
@ -179,7 +232,15 @@
.bitfield PLL_PCIE_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2
.constant SBUS_PCIE_CFG, %0x2243
.constant SBUS_PCIE_COMMAND, %0x2244
.bitfield SBUS_PCIE_COMMAND.Register 0, 8
.bitfield SBUS_PCIE_COMMAND.Address 8, 8
.bitfield SBUS_PCIE_COMMAND.Op 16, 8
.bitfield SBUS_PCIE_COMMAND.Execute 24
.bitfield SBUS_PCIE_COMMAND.Busy 25
.bitfield SBUS_PCIE_COMMAND.ResultCode 26, 3
.constant SBUS_PCIE_REQUEST, %0x2245
.constant SBUS_PCIE_RESPONSE, %0x2246
.constant SBUS_PCIE_SPICO_IN, %0x2247
@ -209,42 +270,64 @@
.constant PCIE_CLK_CTRL, %0x3001
.bitfield PCIE_CLK_CTRL.Nreset 0, 4
.bitfield PCIE_CLK_CTRL.Nreset_0 0
.bitfield PCIE_CLK_CTRL.Nreset_1 1
.bitfield PCIE_CLK_CTRL.Nreset_2 2
.bitfield PCIE_CLK_CTRL.Nreset_3 3
.bitfield PCIE_CLK_CTRL.Nreset_2 1
.bitfield PCIE_CLK_CTRL.Nreset_4 2
.bitfield PCIE_CLK_CTRL.Nreset_6 3
.bitfield PCIE_CLK_CTRL.Enable 4, 4
.bitfield PCIE_CLK_CTRL.Enable_0 4
.bitfield PCIE_CLK_CTRL.Enable_1 5
.bitfield PCIE_CLK_CTRL.Enable_2 6
.bitfield PCIE_CLK_CTRL.Enable_3 7
.bitfield PCIE_CLK_CTRL.Enable_2 5
.bitfield PCIE_CLK_CTRL.Enable_4 6
.bitfield PCIE_CLK_CTRL.Enable_6 7
.bitfield PCIE_CLK_CTRL.Halt 8, 4
.bitfield PCIE_CLK_CTRL.Halt_0 8
.bitfield PCIE_CLK_CTRL.Halt_1 9
.bitfield PCIE_CLK_CTRL.Halt_2 10
.bitfield PCIE_CLK_CTRL.Halt_3 11
.bitfield PCIE_CLK_CTRL.Halt_2 9
.bitfield PCIE_CLK_CTRL.Halt_4 10
.bitfield PCIE_CLK_CTRL.Halt_6 11
.bitfield PCIE_CLK_CTRL.OutMuxSel 12, 8
.bitfield PCIE_CLK_CTRL.OutMuxSel_0 12, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_0 14, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_0 16, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_0 18, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_2 14, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_4 16, 2
.bitfield PCIE_CLK_CTRL.OutMuxSel_6 18, 2
.bitfield PCIE_CLK_CTRL.Mode 20, 12
.bitfield PCIE_CLK_CTRL.Mode_0 20, 3
.bitfield PCIE_CLK_CTRL.Mode_1 23, 3
.bitfield PCIE_CLK_CTRL.Mode_2 26, 3
.bitfield PCIE_CLK_CTRL.Mode_3 29, 3
.bitfield PCIE_CLK_CTRL.Mode_2 23, 3
.bitfield PCIE_CLK_CTRL.Mode_4 26, 3
.bitfield PCIE_CLK_CTRL.Mode_6 29, 3
.constant PCIE_CLK_CTRL_2, %0x3002
.bitfield PCIE_CLK_CTRL_2.XclkTerm 0, 4
.bitfield PCIE_CLK_CTRL_2.XclkTerm_0 0
.bitfield PCIE_CLK_CTRL_2.XclkTerm_1 1
.bitfield PCIE_CLK_CTRL_2.XclkTerm_2 2
.bitfield PCIE_CLK_CTRL_2.XclkTerm_3 3
.bitfield PCIE_CLK_CTRL_2.XclkTerm_2 1
.bitfield PCIE_CLK_CTRL_2.XclkTerm_4 2
.bitfield PCIE_CLK_CTRL_2.XclkTerm_6 3
.bitfield PCIE_CLK_CTRL_2.ClkObs 4, 4
.constant PCIE_CLKMON_RATIO_CFG, %0x3003
.constant PCIE_CLKMON_TOLERANCE_CFG, %0x3004
.constant PCIE_CLKMON_DEADLINES_CFG, %0x3005
.constant PCIE_CLK_STAT, %0x3006
.bitfield PCIE_CLK_STAT.PllLocked 0, 4
.bitfield PCIE_CLK_STAT.PllLocked_0 0
.bitfield PCIE_CLK_STAT.PllLocked_2 1
.bitfield PCIE_CLK_STAT.PllLocked_4 2
.bitfield PCIE_CLK_STAT.PllLocked_6 3
.bitfield PCIE_CLK_STAT.PllFreqChange 4, 4
.bitfield PCIE_CLK_STAT.PllFreqChange_0 4
.bitfield PCIE_CLK_STAT.PllFreqChange_2 5
.bitfield PCIE_CLK_STAT.PllFreqChange_4 6
.bitfield PCIE_CLK_STAT.PllFreqChange_6 7
.bitfield PCIE_CLK_STAT.RefclkSel 8, 4
.bitfield PCIE_CLK_STAT.RefclkSel_0 8
.bitfield PCIE_CLK_STAT.RefclkSel_2 9
.bitfield PCIE_CLK_STAT.RefclkSel_4 10
.bitfield PCIE_CLK_STAT.RefclkSel_6 11
.bitfield PCIE_CLK_STAT.XRefclkValid 12, 4
.bitfield PCIE_CLK_STAT.XRefclkValid_0 12
.bitfield PCIE_CLK_STAT.XRefclkValid_2 13
.bitfield PCIE_CLK_STAT.XRefclkValid_4 14
.bitfield PCIE_CLK_STAT.XRefclkValid_6 15
.constant PCIE_CLK_IP, %0x3007
.constant PCIE_CLK_IM, %0x3008
.constant PCIE_WARM_RESET_DELAY, %0x3009
@ -275,6 +358,21 @@
;; These require offsets to be accessed
.constant PCIE_PF_BASE, %0x100000
.constant PCIE_IB, PCIE_PF_BASE +0x13000
.bitfield PCIE_IB.HotReset 0
.bitfield PCIE_IB.DeviceStateChange 1
.bitfield PCIE_IB.Mailbox 2
.bitfield PCIE_IB.VPD_Request 3
.bitfield PCIE_IB.SramError 4
.bitfield PCIE_IB.PFLR 5
.bitfield PCIE_IB.DataPathReset 6
.bitfield PCIE_IB.OutOfReset 7
.bitfield PCIE_IB.NotInReset 8
.bitfield PCIE_IB.Timeout 9
.bitfield PCIE_IB.VFLR 10
.constant PCIE_IM, PCIE_PF_BASE +0x13001
.constant PCIE_IB, PCIE_PF_BASE +0x13002
.constant PCIE_SERDES_CTRL_0, PCIE_PF_BASE +0x19010
.constant PCIE_SERDES_CTRL_1, PCIE_SERDES_CTRL_0 +2

62
src/instructions/Instruction.cpp
View file

@ -167,7 +167,67 @@ namespace Instruction {
addOperator("POLL_NOTEQUALS", 6, Poll::fromNonEqualTokens);
addOperator("PNE", 6, Poll::fromNonEqualTokens); //TODO: redo
addOperator("SET", 3, Set::fromTokens);
//This allows both static and dynamic calls, with multiple offsets
addOperator("SET", 3, [](const parseOperatorResult &op, const std::vector<Token> &tokens) -> std::unique_ptr<Instruction> {
if (tokens.at(1).getType() == Token::Type::Immediate && tokens.at(2).getType() == Token::Type::Immediate) {
return Set::fromTokens(op, tokens);
} else {
auto c = std::make_unique<Container>("SET op, extended with registers");
//Get register if needed due to offset
if (op.offset1) {
c->addInstruction(std::make_unique<Copy>(AddressWithOffset{(uint32_t) MgmtRegisters::std_SCRATCH_0, 0},
AddressWithOffset{tokens.at(0).getNumericValue(), op.offset1}));
}
//S0 = (Register & ~maskValue)
if (tokens.at(2).getType() == Token::Type::Immediate) {
c->addInstruction(std::make_unique<CalcImm>(Calc::Operation::AND, 0, (uint32_t) MgmtRegisters::std_SCRATCH_0,
op.offset1 ? (uint32_t) MgmtRegisters::std_SCRATCH_0 : tokens.at(
0).getNumericValue(), ~tokens.at(2).getNumericValue()));
} else {
if (op.offset2) {
c->addInstruction(std::make_unique<Copy>(AddressWithOffset{(uint32_t) MgmtRegisters::std_SCRATCH_1, 0},
AddressWithOffset{tokens.at(2).getNumericValue(), op.offset2}));
}
//NOT without offset
c->addInstruction(std::make_unique<Calc>(Calc::Operation::SUB, 0,
(uint32_t) MgmtRegisters::std_SCRATCH_1,
(uint32_t) MgmtRegisters::INTERNAL_REGISTER_ALWAYS_FFFFFFFF,
op.offset2 ? (uint32_t) MgmtRegisters::std_SCRATCH_1 : tokens.at(
2).getNumericValue()));
c->addInstruction(std::make_unique<Calc>(Calc::Operation::AND, 0, (uint32_t) MgmtRegisters::std_SCRATCH_0,
op.offset1 ? (uint32_t) MgmtRegisters::std_SCRATCH_0 : tokens.at(
0).getNumericValue(), (uint32_t) MgmtRegisters::std_SCRATCH_1));
}
//Register = S0 | value
if (tokens.at(1).getType() == Token::Type::Immediate) {
c->addInstruction(std::make_unique<CalcImm>(Calc::Operation::OR, 0,
op.offset1 ? (uint32_t) MgmtRegisters::std_SCRATCH_0 : tokens.at(
0).getNumericValue(), (uint32_t) MgmtRegisters::std_SCRATCH_0,
tokens.at(1).getNumericValue()));
} else {
if (op.offset3) {
c->addInstruction(std::make_unique<Copy>(AddressWithOffset{(uint32_t) MgmtRegisters::std_SCRATCH_1, 0},
AddressWithOffset{tokens.at(1).getNumericValue(), op.offset2}));
}
c->addInstruction(std::make_unique<Calc>(Calc::Operation::OR, 0,
op.offset1 ? (uint32_t) MgmtRegisters::std_SCRATCH_0 : tokens.at(
0).getNumericValue(), (uint32_t) MgmtRegisters::std_SCRATCH_0,
op.offset3 ? (uint32_t) MgmtRegisters::std_SCRATCH_1 : tokens.at(
1).getNumericValue()));
}
//set register if needed due to offset
if (op.offset1) {
c->addInstruction(std::make_unique<Copy>(AddressWithOffset{tokens.at(0).getNumericValue(), op.offset1},
AddressWithOffset{(uint32_t) MgmtRegisters::std_SCRATCH_0, 0}));
}
return std::move(c);
}
});
addOperator("LOOP", 1, Loop::fromTokens);

1
src/instructions/Instruction.h
View file

@ -74,6 +74,7 @@ namespace Instruction {
std::string name;
uint8_t offset1;
uint8_t offset2;
uint8_t offset3;
};
static parseOperatorResult parseOperator(const std::string &op);