DataHoarder
c6d9b910df
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400 lines
13 KiB
NASM
400 lines
13 KiB
NASM
;; Definition of registers found on FM10000 ASIP
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;; Based on Intel datasheet and BSD-3 code.
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.constant FATAL_CODE, %0x0
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.constant LAST_FATAL_CODE, %0x1
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.constant SOFT_RESET, %0x3
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.bitfield SOFT_RESET.ColdReset 0
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.bitfield SOFT_RESET.EPLReset 1
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.bitfield SOFT_RESET.SwitchReset 2
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.bitfield SOFT_RESET.SwitchReady 3
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.bitfield SOFT_RESET.PCIeReset 4, 9
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.bitfield SOFT_RESET.PCIeReset_0 4
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.bitfield SOFT_RESET.PCIeReset_1 5
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.bitfield SOFT_RESET.PCIeReset_2 6
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.bitfield SOFT_RESET.PCIeReset_3 7
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.bitfield SOFT_RESET.PCIeReset_4 8
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.bitfield SOFT_RESET.PCIeReset_5 9
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.bitfield SOFT_RESET.PCIeReset_6 10
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.bitfield SOFT_RESET.PCIeReset_7 11
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.bitfield SOFT_RESET.PCIeReset_8 12
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.bitfield SOFT_RESET.PCIeActive 13, 9
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.bitfield SOFT_RESET.PCIeActive_0 13
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.bitfield SOFT_RESET.PCIeActive_1 14
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.bitfield SOFT_RESET.PCIeActive_2 15
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.bitfield SOFT_RESET.PCIeActive_3 16
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.bitfield SOFT_RESET.PCIeActive_4 17
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.bitfield SOFT_RESET.PCIeActive_5 18
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.bitfield SOFT_RESET.PCIeActive_6 19
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.bitfield SOFT_RESET.PCIeActive_7 20
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.bitfield SOFT_RESET.PCIeActive_8 21
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.constant DEVICE_CFG, %0x4
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.bitfield DEVICE_CFG.PCIeMode 0, 4
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.bitfield DEVICE_CFG.PCIeMode_0 0
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.bitfield DEVICE_CFG.PCIeMode_2 1
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.bitfield DEVICE_CFG.PCIeMode_4 2
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.bitfield DEVICE_CFG.PCIeMode_6 3
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.bitfield DEVICE_CFG.Eth100GDisabled 4
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.bitfield DEVICE_CFG.FeatureCode 5, 2
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.bitfield DEVICE_CFG.PCIeEnable 7, 9
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.bitfield DEVICE_CFG.PCIeEnable_0 7
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.bitfield DEVICE_CFG.PCIeEnable_1 8
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.bitfield DEVICE_CFG.PCIeEnable_2 9
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.bitfield DEVICE_CFG.PCIeEnable_3 10
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.bitfield DEVICE_CFG.PCIeEnable_4 11
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.bitfield DEVICE_CFG.PCIeEnable_5 12
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.bitfield DEVICE_CFG.PCIeEnable_6 13
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.bitfield DEVICE_CFG.PCIeEnable_7 14
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.bitfield DEVICE_CFG.PCIeEnable_8 15
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.bitfield DEVICE_CFG.SystimeClockSource 16
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.constant RESET_CFG, %0x5
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.constant WATCHDOG_CFG, %0x6
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.constant MGMT_SCRATCH_0, %0x8
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.constant MGMT_SCRATCH_1, MGMT_SCRATCH_0 +1
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.constant VITAL_PRODUCT_DATA, %0x304
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.bitfield VITAL_PRODUCT_DATA.PartNumber 0, 16
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;; These are the interrupts detect/mask that exist. All use same bitfields
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.constant GLOBAL_INTERRUPT_DETECT_0, %0x400
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.constant GLOBAL_INTERRUPT_DETECT_1, %0x401
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.constant INTERRUPT_MASK_INT_0, %0x402
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.constant INTERRUPT_MASK_INT_1, %0x403
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.constant INTERRUPT_MASK_PCIE_0, %0x420
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.constant INTERRUPT_MASK_PCIE_1, %0x422
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.constant INTERRUPT_MASK_PCIE_2, %0x424
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.constant INTERRUPT_MASK_PCIE_3, %0x426
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.constant INTERRUPT_MASK_PCIE_4, %0x428
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.constant INTERRUPT_MASK_PCIE_5, %0x42a
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.constant INTERRUPT_MASK_PCIE_6, %0x42c
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.constant INTERRUPT_MASK_PCIE_7, %0x42e
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.constant INTERRUPT_MASK_PCIE_8, %0x431
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.constant INTERRUPT_MASK_FIBM_0, %0x440
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.constant INTERRUPT_MASK_FIBM_1, %0x441
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.constant INTERRUPT_MASK_BSM_0, %0x442
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.constant INTERRUPT_MASK_BSM_1, %0x443
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.bitfield INTERRUPTS_0.PCIE_BSM 0, 9
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.bitfield INTERRUPTS_0.PCIE_BSM_0 0
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.bitfield INTERRUPTS_0.PCIE_BSM_1 1
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.bitfield INTERRUPTS_0.PCIE_BSM_2 2
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.bitfield INTERRUPTS_0.PCIE_BSM_3 3
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.bitfield INTERRUPTS_0.PCIE_BSM_4 4
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.bitfield INTERRUPTS_0.PCIE_BSM_5 5
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.bitfield INTERRUPTS_0.PCIE_BSM_6 6
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.bitfield INTERRUPTS_0.PCIE_BSM_7 7
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.bitfield INTERRUPTS_0.PCIE_BSM_8 8
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.bitfield INTERRUPTS_0.PCIE 9, 9
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.bitfield INTERRUPTS_0.PCIE_0 9
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.bitfield INTERRUPTS_0.PCIE_1 10
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.bitfield INTERRUPTS_0.PCIE_2 11
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.bitfield INTERRUPTS_0.PCIE_3 12
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.bitfield INTERRUPTS_0.PCIE_4 13
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.bitfield INTERRUPTS_0.PCIE_5 14
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.bitfield INTERRUPTS_0.PCIE_6 15
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.bitfield INTERRUPTS_0.PCIE_7 16
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.bitfield INTERRUPTS_0.PCIE_8 17
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.bitfield INTERRUPTS_0.EPL 18, 9
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.bitfield INTERRUPTS_0.EPL_0 18
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.bitfield INTERRUPTS_0.EPL_1 19
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.bitfield INTERRUPTS_0.EPL_2 20
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.bitfield INTERRUPTS_0.EPL_3 21
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.bitfield INTERRUPTS_0.EPL_4 22
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.bitfield INTERRUPTS_0.EPL_5 23
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.bitfield INTERRUPTS_0.EPL_6 24
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.bitfield INTERRUPTS_0.EPL_7 25
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.bitfield INTERRUPTS_0.EPL_8 26
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.bitfield INTERRUPTS_0.TUNNEL 27, 2
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.bitfield INTERRUPTS_0.TUNNEL_0 27
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.bitfield INTERRUPTS_0.TUNNEL_1 28
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.bitfield INTERRUPTS_0.CORE, 29
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.bitfield INTERRUPTS_0.SOFTWARE, 30
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.bitfield INTERRUPTS_0.GPIO, 31
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.bitfield INTERRUPTS_1.I2C, 0
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.bitfield INTERRUPTS_1.MDIO, 1
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.bitfield INTERRUPTS_1.CRM, 2
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.bitfield INTERRUPTS_1.FH_TAIL, 3
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.bitfield INTERRUPTS_1.FH_HEAD, 4
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.bitfield INTERRUPTS_1.SBUS_EPL, 5
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.bitfield INTERRUPTS_1.SBUS_PCIE, 6
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.bitfield INTERRUPTS_1.PINS, 7
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.bitfield INTERRUPTS_1.FIBM, 8
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.bitfield INTERRUPTS_1.BSM, 9
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.bitfield INTERRUPTS_1.XCLK, 10
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.constant CORE_INTERRUPT_DETECT, %0x444
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.constant CORE_INTERRUPT_MASK, %0x445
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.constant SRAM_ERR_IP_0, %0x446
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.constant SRAM_ERR_IP_1, %0x447
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.constant SRAM_ERR_IM_0, %0x448
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.constant SRAM_ERR_IM_1, %0x449
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.constant PINS_STAT, %0x44a
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.constant PINS_IP, %0x44b
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.constant PINS_IM, %0x44c
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.constant SW_IP, %0x44d
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.constant SW_IM, %0x44e
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.constant SW_TEST_AND_SET, %0x44f
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.constant LSM_CLKOBS_CTRL, %0x450
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.constant CHIP_VERSION, %0x452
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.bitfield CHIP_VERSION.Version 0, 7
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.constant BSM_SCRATCH_START, %0x800
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.constant BSM_SCRATCH_END, BSM_SCRATCH_START +0x400
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.constant BSM_CTRL, %0x000C00
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.constant BSM_ARGS, %0x000C01
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.constant BSM_ADDR_OFFSET_0, %0x000C04
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.constant BSM_ADDR_OFFSET_1, BSM_ADDR_OFFSET_0 +1
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.constant BSM_ADDR_OFFSET_2, BSM_ADDR_OFFSET_0 +2
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.constant BSM_ADDR_OFFSET_3, BSM_ADDR_OFFSET_0 +3
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.constant BSM_COUNTER_0, %0x000C08
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.constant BSM_COUNTER_1, BSM_COUNTER_0 +1
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.constant BSM_SRAM_CTRL, %0x000C0A
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.constant BSM_IP, %0x000C0B
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.constant BSM_IM, %0x000C0C
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.constant PIN_STRAP_STAT, %0x000C0D
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.constant FUSE_DATA_0, %0x000C0E
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.constant FUSE_DATA_1, %0x000C0F
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.constant BIST_CTRL_0, %0x000C10
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.constant BIST_CTRL_1, %0x000C11
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.constant REI_CTRL, %0x000C12
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.constant REI_STAT, %0x000C13
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.constant GPIO_CFG, %0x000C15
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.constant GPIO_DATA, %0x000C16
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.constant GPIO_IP, %0x000C17
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.constant GPIO_IM, %0x000C18
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.constant I2C_CFG, %0x000C19
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.constant I2C_DATA_0, %0x000C1C
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.constant I2C_DATA_1, %0x000C1D
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.constant I2C_DATA_2, %0x000C1E
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.constant I2C_CTRL, %0x000C20
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.constant MDIO_CFG, %0x000C22
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.constant MDIO_DATA, %0x000C23
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.constant MDIO_CTRL, %0x000C24
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.constant SPI_TX_DATA, %0x000C26
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.constant SPI_RX_DATA, %0x000C27
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.constant SPI_HEADER, %0x000C28
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.constant SPI_CTRL, %0x000C29
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.constant LED_CFG, %0x000C2B
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.constant SCAN_DATA_IN, %0x000C2D
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.constant CRM_DATA_START, %0x001000 ;; 2048 entries, each one 2 words
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.constant CRM_DATA_END, %0x001FFF
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.constant CRM_CTRL, %0x002000
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.constant CRM_STATUS, %0x002001
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.constant CRM_TIME, %0x002002
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.constant CRM_SRAM_CTRL, %0x002004
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.constant CRM_IP, %0x002008
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.constant CRM_IM, %0x00200C
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.constant CRM_COMMAND_START, %0x002080 ;; 64 entries, each one 2 words
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.constant CRM_COMMAND_END, %0x0020FF
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.constant CRM_REGISTER_START, %0x002100 ;; 64 entries, each one 2 words
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.constant CRM_REGISTER_END, %0x00217F
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.constant CRM_PERIOD_START, %0x002180 ;; 64 entries, each one 2 words
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.constant CRM_PERIOD_END, %0x0021FF
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.constant CRM_PARAM_START, %0x002200 ;; 64 entries, each one 1 words
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.constant CRM_PARAM_END, %0x002240
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.constant PLL_PCIE_CTRL, %0x2241
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.bitfield PLL_PCIE_CTRL.Nreset 0
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.bitfield PLL_PCIE_CTRL.NEnable 1
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.bitfield PLL_PCIE_CTRL.Halt 2
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.bitfield PLL_PCIE_CTRL.RefDiv 3, 6
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.bitfield PLL_PCIE_CTRL.FbDiv4 9
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.bitfield PLL_PCIE_CTRL.FbDiv255 10, 8
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.bitfield PLL_PCIE_CTRL.OutDiv 18, 6
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.bitfield PLL_PCIE_CTRL.OutMuxSel 24, 3
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.constant PLL_PCIE_STAT, %0x2242
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.bitfield PLL_PCIE_STAT.PllLocked 0
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.bitfield PLL_PCIE_STAT.PllFreqChange 1
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.bitfield PLL_PCIE_STAT.MiscCtrl.FastCalibrationMode 2
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.bitfield PLL_PCIE_STAT.MiscCtrl.AsyncPLLLoadSignal 6
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.bitfield PLL_PCIE_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2
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.constant SBUS_PCIE_CFG, %0x2243
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.constant SBUS_PCIE_COMMAND, %0x2244
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.bitfield SBUS_PCIE_COMMAND.Register 0, 8
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.bitfield SBUS_PCIE_COMMAND.Address 8, 8
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.bitfield SBUS_PCIE_COMMAND.Op 16, 8
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.bitfield SBUS_PCIE_COMMAND.Execute 24
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.bitfield SBUS_PCIE_COMMAND.Busy 25
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.bitfield SBUS_PCIE_COMMAND.ResultCode 26, 3
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.constant SBUS_PCIE_REQUEST, %0x2245
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.constant SBUS_PCIE_RESPONSE, %0x2246
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.constant SBUS_PCIE_SPICO_IN, %0x2247
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.constant SBUS_PCIE_SPICO_OUT, %0x2248
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.constant SBUS_PCIE_IP, %0x2249
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.constant SBUS_PCIE_IM, %0x224a
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.constant SYSTIME_CFG_0, %0x224C
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.constant SYSTIME_CFG_1, %0x224D
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.constant SYSTIME_0, %0x224E
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.constant SYSTIME_1, %0x224F
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.constant SYSTIME0_0, %0x2250
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.constant SYSTIME0_1, %0x2251
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.constant SYSTIME_PULSE_0, %0x2252
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.constant SYSTIME_PULSE_1, %0x2253
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.constant SYSTIME_CAPTURE_0_0, %0x2254
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.constant SYSTIME_CAPTURE_0_1, %0x2255
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.constant SYSTIME_CAPTURE_1_0, %0x2256
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.constant SYSTIME_CAPTURE_1_1, %0x2257
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.constant SYSTIME_CAPTURE_2_0, %0x2258
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.constant SYSTIME_CAPTURE_2_1, %0x2259
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.constant SYSTIME_CAPTURE_3_0, %0x225a
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.constant SYSTIME_CAPTURE_3_1, %0x225b
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.constant PCIE_XPLL_CTRL, %0x3000
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.constant PCIE_CLK_CTRL, %0x3001
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.bitfield PCIE_CLK_CTRL.Nreset 0, 4
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.bitfield PCIE_CLK_CTRL.Nreset_0 0
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.bitfield PCIE_CLK_CTRL.Nreset_2 1
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.bitfield PCIE_CLK_CTRL.Nreset_4 2
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.bitfield PCIE_CLK_CTRL.Nreset_6 3
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.bitfield PCIE_CLK_CTRL.Enable 4, 4
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.bitfield PCIE_CLK_CTRL.Enable_0 4
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.bitfield PCIE_CLK_CTRL.Enable_2 5
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.bitfield PCIE_CLK_CTRL.Enable_4 6
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.bitfield PCIE_CLK_CTRL.Enable_6 7
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.bitfield PCIE_CLK_CTRL.Halt 8, 4
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.bitfield PCIE_CLK_CTRL.Halt_0 8
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.bitfield PCIE_CLK_CTRL.Halt_2 9
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.bitfield PCIE_CLK_CTRL.Halt_4 10
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.bitfield PCIE_CLK_CTRL.Halt_6 11
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.bitfield PCIE_CLK_CTRL.OutMuxSel 12, 8
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.bitfield PCIE_CLK_CTRL.OutMuxSel_0 12, 2
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.bitfield PCIE_CLK_CTRL.OutMuxSel_2 14, 2
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.bitfield PCIE_CLK_CTRL.OutMuxSel_4 16, 2
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.bitfield PCIE_CLK_CTRL.OutMuxSel_6 18, 2
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.bitfield PCIE_CLK_CTRL.Mode 20, 12
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.bitfield PCIE_CLK_CTRL.Mode_0 20, 3
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.bitfield PCIE_CLK_CTRL.Mode_2 23, 3
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.bitfield PCIE_CLK_CTRL.Mode_4 26, 3
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.bitfield PCIE_CLK_CTRL.Mode_6 29, 3
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.constant PCIE_CLK_CTRL_2, %0x3002
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.bitfield PCIE_CLK_CTRL_2.XclkTerm 0, 4
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.bitfield PCIE_CLK_CTRL_2.XclkTerm_0 0
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.bitfield PCIE_CLK_CTRL_2.XclkTerm_2 1
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.bitfield PCIE_CLK_CTRL_2.XclkTerm_4 2
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.bitfield PCIE_CLK_CTRL_2.XclkTerm_6 3
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.bitfield PCIE_CLK_CTRL_2.ClkObs 4, 4
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.constant PCIE_CLKMON_RATIO_CFG, %0x3003
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.constant PCIE_CLKMON_TOLERANCE_CFG, %0x3004
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.constant PCIE_CLKMON_DEADLINES_CFG, %0x3005
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.constant PCIE_CLK_STAT, %0x3006
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.bitfield PCIE_CLK_STAT.PllLocked 0, 4
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.bitfield PCIE_CLK_STAT.PllLocked_0 0
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.bitfield PCIE_CLK_STAT.PllLocked_2 1
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.bitfield PCIE_CLK_STAT.PllLocked_4 2
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.bitfield PCIE_CLK_STAT.PllLocked_6 3
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.bitfield PCIE_CLK_STAT.PllFreqChange 4, 4
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.bitfield PCIE_CLK_STAT.PllFreqChange_0 4
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.bitfield PCIE_CLK_STAT.PllFreqChange_2 5
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.bitfield PCIE_CLK_STAT.PllFreqChange_4 6
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.bitfield PCIE_CLK_STAT.PllFreqChange_6 7
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.bitfield PCIE_CLK_STAT.RefclkSel 8, 4
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.bitfield PCIE_CLK_STAT.RefclkSel_0 8
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.bitfield PCIE_CLK_STAT.RefclkSel_2 9
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.bitfield PCIE_CLK_STAT.RefclkSel_4 10
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.bitfield PCIE_CLK_STAT.RefclkSel_6 11
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.bitfield PCIE_CLK_STAT.XRefclkValid 12, 4
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.bitfield PCIE_CLK_STAT.XRefclkValid_0 12
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.bitfield PCIE_CLK_STAT.XRefclkValid_2 13
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.bitfield PCIE_CLK_STAT.XRefclkValid_4 14
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.bitfield PCIE_CLK_STAT.XRefclkValid_6 15
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.constant PCIE_CLK_IP, %0x3007
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.constant PCIE_CLK_IM, %0x3008
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.constant PCIE_WARM_RESET_DELAY, %0x3009
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.constant PORTS_MGMT_BASE_ADDRESS, %0xE8000
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.constant PLL_EPL_CTRL, %0xE8000
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.constant PLL_EPL_STAT, %0xE8001
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.bitfield PLL_EPL_STAT.PllLocked 0
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.bitfield PLL_EPL_STAT.PllFreqChange 1
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.bitfield PLL_EPL_STAT.MiscCtrl.FastCalibrationMode 2
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.bitfield PLL_EPL_STAT.MiscCtrl.AsyncPLLLoadSignal 6
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.bitfield PLL_EPL_STAT.MiscCtrl.InitialCoarseThermalBits 8, 2
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.constant PLL_FABRIC_CTRL, %0xE8002
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.constant PLL_FABRIC_STAT, %0xE8003
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.constant PLL_FABRIC_LOCK, %0xE8004
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.constant SBUS_EPL_CFG, %0xE8005
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.constant SBUS_EPL_COMMAND, %0xE8006
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.constant SBUS_EPL_REQUEST, %0xE8007
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.constant SBUS_EPL_RESPONSE, %0xE8008
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.constant SBUS_EPL_SPICO_IN, %0xE8009
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.constant SBUS_EPL_SPICO_OUT, %0xE800a
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.constant SBUS_EPL_IP, %0xE800b
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.constant SBUS_EPL_IM, %0xE800c
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.constant PM_CLKOBS_CTRL, %0xE8012
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;; These require offsets to be accessed
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.constant PCIE_PF_BASE, %0x100000
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.constant PCIE_PF_OFFSET, 0x100000
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.constant PCIE_IP, PCIE_PF_BASE +0x13000
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.bitfield PCIE_IP.HotReset 0
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.bitfield PCIE_IP.DeviceStateChange 1
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.bitfield PCIE_IP.Mailbox 2
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.bitfield PCIE_IP.VPD_Request 3
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.bitfield PCIE_IP.SramError 4
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.bitfield PCIE_IP.PFLR 5
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.bitfield PCIE_IP.DataPathReset 6
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.bitfield PCIE_IP.OutOfReset 7
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.bitfield PCIE_IP.NotInReset 8
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.bitfield PCIE_IP.Timeout 9
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.bitfield PCIE_IP.VFLR 10
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.constant PCIE_IM, PCIE_PF_BASE +0x13001
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.constant PCIE_IB, PCIE_PF_BASE +0x13002
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.bitfield PCIE_SERDES_CTRL_a.Interrupt 1
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.bitfield PCIE_SERDES_CTRL_a.InProgress 2
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.bitfield PCIE_SERDES_CTRL_a.InterruptCode 16, 16
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.bitfield PCIE_SERDES_CTRL_b.DataWrite 0, 16
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.bitfield PCIE_SERDES_CTRL_b.DataRead 16, 16
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.constant PCIE_SERDES_CTRL_0a, PCIE_PF_BASE +0x19010
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.constant PCIE_SERDES_CTRL_0b, PCIE_SERDES_CTRL_0a +1
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.constant PCIE_SERDES_CTRL_1a, PCIE_SERDES_CTRL_0a +2
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.constant PCIE_SERDES_CTRL_1b, PCIE_SERDES_CTRL_1a +1
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.constant PCIE_SERDES_CTRL_2a, PCIE_SERDES_CTRL_1a +2
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.constant PCIE_SERDES_CTRL_2b, PCIE_SERDES_CTRL_2a +1
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.constant PCIE_SERDES_CTRL_3a, PCIE_SERDES_CTRL_2a +2
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.constant PCIE_SERDES_CTRL_3b, PCIE_SERDES_CTRL_3a +1
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.constant PCIE_SERDES_CTRL_4a, PCIE_SERDES_CTRL_3a +2
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.constant PCIE_SERDES_CTRL_4b, PCIE_SERDES_CTRL_4a +1
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.constant PCIE_SERDES_CTRL_5a, PCIE_SERDES_CTRL_4a +2
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.constant PCIE_SERDES_CTRL_5b, PCIE_SERDES_CTRL_5a +1
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.constant PCIE_SERDES_CTRL_6a, PCIE_SERDES_CTRL_5a +2
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.constant PCIE_SERDES_CTRL_6b, PCIE_SERDES_CTRL_6a +1
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.constant PCIE_SERDES_CTRL_7a, PCIE_SERDES_CTRL_6a +2
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.constant PCIE_SERDES_CTRL_7b, PCIE_SERDES_CTRL_7a +1 |