Use direct register and scratchpad under bytecode execution
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SHA256:OLTRf6Fl87G52SiR7sWLGNzlJt4WOX+tfI2yxo0z7xk
151
bytecode.go
151
bytecode.go
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@ -1,22 +1,17 @@
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package randomx
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import (
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"encoding/binary"
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"git.gammaspectra.live/P2Pool/go-randomx/v2/asm"
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"math"
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"math/bits"
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)
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type ByteCodeInstruction struct {
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dst, src byte
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idst, isrc *uint64
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fdst, fsrc *[2]float64
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imm uint64
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simm int64
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Opcode ByteCodeInstructionOp
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target int16
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shift uint8
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memMask uint32
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dst, src byte
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immB uint8
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Opcode ByteCodeInstructionOp
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memMask uint32
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imm uint64
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/*
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union {
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int_reg_t* idst;
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@ -40,112 +35,127 @@ type ByteCodeInstruction struct {
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}
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func (i ByteCodeInstruction) getScratchpadSrcAddress() uint64 {
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return (*i.isrc + i.imm) & uint64(i.memMask)
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func (i ByteCodeInstruction) jumpTarget() int {
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return int(int16((uint16(i.immB) << 8) | uint16(i.dst)))
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}
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func (i ByteCodeInstruction) getScratchpadZeroAddress() uint64 {
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return i.imm & uint64(i.memMask)
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func (i ByteCodeInstruction) getScratchpadAddress(ptr uint64) uint32 {
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return uint32(ptr+i.imm) & i.memMask
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}
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func (i ByteCodeInstruction) getScratchpadDestAddress() uint64 {
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return (*i.idst + i.imm) & uint64(i.memMask)
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func (i ByteCodeInstruction) getScratchpadZeroAddress() uint32 {
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return uint32(i.imm) & i.memMask
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}
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type ByteCode [RANDOMX_PROGRAM_SIZE]ByteCodeInstruction
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func (c *ByteCode) Interpret(vm *VM) {
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func (c *ByteCode) Execute(f RegisterFile, pad *ScratchPad, eMask [2]uint64) RegisterFile {
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for pc := 0; pc < RANDOMX_PROGRAM_SIZE; pc++ {
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ibc := c[pc]
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ibc := &c[pc]
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switch ibc.Opcode {
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case VM_IADD_RS:
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm
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f.r[ibc.dst] += (f.r[ibc.src] << ibc.immB) + ibc.imm
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case VM_IADD_M:
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*ibc.idst += vm.Load64(ibc.getScratchpadSrcAddress())
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f.r[ibc.dst] += pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src]))
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case VM_IADD_MZ:
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*ibc.idst += vm.Load64(ibc.getScratchpadZeroAddress())
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f.r[ibc.dst] += pad.Load64(uint32(ibc.imm))
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case VM_ISUB_R:
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*ibc.idst -= *ibc.isrc
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f.r[ibc.dst] -= f.r[ibc.src]
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case VM_ISUB_I:
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f.r[ibc.dst] -= ibc.imm
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case VM_ISUB_M:
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*ibc.idst -= vm.Load64(ibc.getScratchpadSrcAddress())
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f.r[ibc.dst] -= pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src]))
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case VM_ISUB_MZ:
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*ibc.idst -= vm.Load64(ibc.getScratchpadZeroAddress())
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f.r[ibc.dst] -= pad.Load64(uint32(ibc.imm))
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case VM_IMUL_R:
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f.r[ibc.dst] *= f.r[ibc.src]
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case VM_IMUL_I:
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// also handles imul_rcp
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*ibc.idst *= *ibc.isrc
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f.r[ibc.dst] *= ibc.imm
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case VM_IMUL_M:
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*ibc.idst *= vm.Load64(ibc.getScratchpadSrcAddress())
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f.r[ibc.dst] *= pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src]))
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case VM_IMUL_MZ:
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*ibc.idst *= vm.Load64(ibc.getScratchpadZeroAddress())
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f.r[ibc.dst] *= pad.Load64(uint32(ibc.imm))
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case VM_IMULH_R:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, *ibc.isrc)
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f.r[ibc.dst], _ = bits.Mul64(f.r[ibc.dst], f.r[ibc.src])
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case VM_IMULH_M:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadSrcAddress()))
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f.r[ibc.dst], _ = bits.Mul64(f.r[ibc.dst], pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src])))
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case VM_IMULH_MZ:
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*ibc.idst, _ = bits.Mul64(*ibc.idst, vm.Load64(ibc.getScratchpadZeroAddress()))
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f.r[ibc.dst], _ = bits.Mul64(f.r[ibc.dst], pad.Load64(uint32(ibc.imm)))
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case VM_ISMULH_R:
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*ibc.idst = smulh(int64(*ibc.idst), int64(*ibc.isrc))
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f.r[ibc.dst] = smulh(int64(f.r[ibc.dst]), int64(f.r[ibc.src]))
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case VM_ISMULH_M:
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*ibc.idst = smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadSrcAddress())))
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f.r[ibc.dst] = smulh(int64(f.r[ibc.dst]), int64(pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src]))))
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case VM_ISMULH_MZ:
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*ibc.idst = smulh(int64(*ibc.idst), int64(vm.Load64(ibc.getScratchpadZeroAddress())))
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f.r[ibc.dst] = smulh(int64(f.r[ibc.dst]), int64(pad.Load64(uint32(ibc.imm))))
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case VM_INEG_R:
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*ibc.idst = (^(*ibc.idst)) + 1 // 2's complement negative
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//f.r[ibc.dst] = (^(f.r[ibc.dst])) + 1 // 2's complement negative
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f.r[ibc.dst] = -f.r[ibc.dst]
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case VM_IXOR_R:
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*ibc.idst ^= *ibc.isrc
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f.r[ibc.dst] ^= f.r[ibc.src]
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case VM_IXOR_I:
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f.r[ibc.dst] ^= ibc.imm
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case VM_IXOR_M:
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*ibc.idst ^= vm.Load64(ibc.getScratchpadSrcAddress())
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f.r[ibc.dst] ^= pad.Load64(ibc.getScratchpadAddress(f.r[ibc.src]))
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case VM_IXOR_MZ:
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*ibc.idst ^= vm.Load64(ibc.getScratchpadZeroAddress())
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f.r[ibc.dst] ^= pad.Load64(uint32(ibc.imm))
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case VM_IROR_R:
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*ibc.idst = bits.RotateLeft64(*ibc.idst, 0-int(*ibc.isrc&63))
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f.r[ibc.dst] = bits.RotateLeft64(f.r[ibc.dst], 0-int(f.r[ibc.src]&63))
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case VM_IROR_I:
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//todo: can merge into VM_IROL_I
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f.r[ibc.dst] = bits.RotateLeft64(f.r[ibc.dst], 0-int(ibc.imm&63))
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case VM_IROL_R:
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*ibc.idst = bits.RotateLeft64(*ibc.idst, int(*ibc.isrc&63))
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f.r[ibc.dst] = bits.RotateLeft64(f.r[ibc.dst], int(f.r[ibc.src]&63))
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case VM_IROL_I:
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f.r[ibc.dst] = bits.RotateLeft64(f.r[ibc.dst], int(ibc.imm&63))
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case VM_ISWAP_R:
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*ibc.idst, *ibc.isrc = *ibc.isrc, *ibc.idst
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case VM_FSWAP_R:
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ibc.fdst[HIGH], ibc.fdst[LOW] = ibc.fdst[LOW], ibc.fdst[HIGH]
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f.r[ibc.dst], f.r[ibc.src] = f.r[ibc.src], f.r[ibc.dst]
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case VM_FSWAP_RF:
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f.f[ibc.dst][HIGH], f.f[ibc.dst][LOW] = f.f[ibc.dst][LOW], f.f[ibc.dst][HIGH]
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case VM_FSWAP_RE:
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f.e[ibc.dst][HIGH], f.e[ibc.dst][LOW] = f.e[ibc.dst][LOW], f.e[ibc.dst][HIGH]
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case VM_FADD_R:
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ibc.fdst[LOW] += ibc.fsrc[LOW]
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ibc.fdst[HIGH] += ibc.fsrc[HIGH]
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f.f[ibc.dst][LOW] += f.a[ibc.src][LOW]
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f.f[ibc.dst][HIGH] += f.a[ibc.src][HIGH]
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case VM_FADD_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] += lo
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ibc.fdst[HIGH] += hi
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lo, hi := pad.Load32F(ibc.getScratchpadAddress(f.r[ibc.src]))
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f.f[ibc.dst][LOW] += lo
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f.f[ibc.dst][HIGH] += hi
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case VM_FSUB_R:
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ibc.fdst[LOW] -= ibc.fsrc[LOW]
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ibc.fdst[HIGH] -= ibc.fsrc[HIGH]
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f.f[ibc.dst][LOW] -= f.a[ibc.src][LOW]
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f.f[ibc.dst][HIGH] -= f.a[ibc.src][HIGH]
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case VM_FSUB_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] -= lo
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ibc.fdst[HIGH] -= hi
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lo, hi := pad.Load32F(ibc.getScratchpadAddress(f.r[ibc.src]))
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f.f[ibc.dst][LOW] -= lo
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f.f[ibc.dst][HIGH] -= hi
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case VM_FSCAL_R:
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// no dependent on rounding modes
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ibc.fdst[LOW] = math.Float64frombits(math.Float64bits(ibc.fdst[LOW]) ^ 0x80F0000000000000)
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ibc.fdst[HIGH] = math.Float64frombits(math.Float64bits(ibc.fdst[HIGH]) ^ 0x80F0000000000000)
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f.f[ibc.dst][LOW] = math.Float64frombits(math.Float64bits(f.f[ibc.dst][LOW]) ^ 0x80F0000000000000)
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f.f[ibc.dst][HIGH] = math.Float64frombits(math.Float64bits(f.f[ibc.dst][HIGH]) ^ 0x80F0000000000000)
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case VM_FMUL_R:
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ibc.fdst[LOW] *= ibc.fsrc[LOW]
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ibc.fdst[HIGH] *= ibc.fsrc[HIGH]
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f.e[ibc.dst][LOW] *= f.a[ibc.src][LOW]
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f.e[ibc.dst][HIGH] *= f.a[ibc.src][HIGH]
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case VM_FDIV_M:
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lo, hi := vm.Load32F(ibc.getScratchpadSrcAddress())
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ibc.fdst[LOW] /= MaskRegisterExponentMantissa(lo, vm.config.eMask[LOW])
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ibc.fdst[HIGH] /= MaskRegisterExponentMantissa(hi, vm.config.eMask[HIGH])
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lo, hi := pad.Load32F(ibc.getScratchpadAddress(f.r[ibc.src]))
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f.e[ibc.dst][LOW] /= MaskRegisterExponentMantissa(lo, eMask[LOW])
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f.e[ibc.dst][HIGH] /= MaskRegisterExponentMantissa(hi, eMask[HIGH])
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case VM_FSQRT_R:
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ibc.fdst[LOW] = math.Sqrt(ibc.fdst[LOW])
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ibc.fdst[HIGH] = math.Sqrt(ibc.fdst[HIGH])
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f.e[ibc.dst][LOW] = math.Sqrt(f.e[ibc.dst][LOW])
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f.e[ibc.dst][HIGH] = math.Sqrt(f.e[ibc.dst][HIGH])
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case VM_CBRANCH:
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*ibc.isrc += ibc.imm
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if (*ibc.isrc & uint64(ibc.memMask)) == 0 {
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pc = int(ibc.target)
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f.r[ibc.src] += ibc.imm
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if (f.r[ibc.src] & uint64(ibc.memMask)) == 0 {
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pc = ibc.jumpTarget()
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}
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case VM_CFROUND:
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tmp := (bits.RotateLeft64(*ibc.isrc, 0-int(ibc.imm))) % 4 // rotate right
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tmp := (bits.RotateLeft64(f.r[ibc.src], 0-int(ibc.imm))) % 4 // rotate right
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asm.SetRoundingMode(asm.RoundingMode(tmp))
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case VM_ISTORE:
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binary.LittleEndian.PutUint64(vm.ScratchPad[(*ibc.idst+ibc.imm)&uint64(ibc.memMask):], *ibc.isrc)
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pad.Store64(ibc.getScratchpadAddress(f.r[ibc.dst]), f.r[ibc.src])
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case VM_NOP: // we do nothing
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}
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}
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return f
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}
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type ByteCodeInstructionOp int
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@ -156,9 +166,11 @@ const (
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VM_IADD_M
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VM_IADD_MZ
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VM_ISUB_R
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VM_ISUB_I
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VM_ISUB_M
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VM_ISUB_MZ
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VM_IMUL_R
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VM_IMUL_I
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VM_IMUL_M
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VM_IMUL_MZ
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VM_IMULH_R
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@ -167,15 +179,18 @@ const (
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VM_ISMULH_R
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VM_ISMULH_M
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VM_ISMULH_MZ
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VM_IMUL_RCP
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VM_INEG_R
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VM_IXOR_R
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VM_IXOR_I
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VM_IXOR_M
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VM_IXOR_MZ
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VM_IROR_R
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VM_IROR_I
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VM_IROL_R
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VM_IROL_I
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VM_ISWAP_R
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VM_FSWAP_R
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VM_FSWAP_RF
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VM_FSWAP_RE
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VM_FADD_R
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VM_FADD_M
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VM_FSUB_R
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@ -87,7 +87,7 @@ const ScratchpadL3Mask = (ScratchpadL3 - 1) * 8
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const ScratchpadL3Mask64 = (ScratchpadL3/8 - 1) * 64
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const CONDITIONOFFSET = RANDOMX_JUMP_OFFSET
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const CONDITIONMASK = ((1 << RANDOMX_JUMP_BITS) - 1)
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const CONDITIONMASK = (1 << RANDOMX_JUMP_BITS) - 1
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const STOREL3CONDITION = 14
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const mantissaSize = 52
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20
vm.go
20
vm.go
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@ -47,7 +47,7 @@ type VM struct {
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StateStart [64]byte
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buffer [RANDOMX_PROGRAM_SIZE*8 + 16*8]byte // first 128 bytes are entropy below rest are program bytes
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Prog []byte
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ScratchPad [ScratchpadSize]byte
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ScratchPad ScratchPad
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ByteCode ByteCode
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@ -126,22 +126,22 @@ func (vm *VM) Run(input_hash [64]byte) {
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spAddr1 &= ScratchpadL3Mask64
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for i := uint64(0); i < RegistersCount; i++ {
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vm.reg.r[i] ^= vm.Load64(spAddr0 + 8*i)
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vm.reg.r[i] ^= vm.ScratchPad.Load64(uint32(spAddr0 + 8*i))
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}
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.f[i] = vm.Load32FA(spAddr1 + 8*i)
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vm.reg.f[i] = vm.ScratchPad.Load32FA(uint32(spAddr1 + 8*i))
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}
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.e[i] = vm.Load32FA(spAddr1 + 8*(i+RegistersCountFloat))
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vm.reg.e[i] = vm.ScratchPad.Load32FA(uint32(spAddr1 + 8*(i+RegistersCountFloat)))
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vm.reg.e[i][LOW] = MaskRegisterExponentMantissa(vm.reg.e[i][LOW], vm.config.eMask[LOW])
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vm.reg.e[i][HIGH] = MaskRegisterExponentMantissa(vm.reg.e[i][HIGH], vm.config.eMask[HIGH])
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}
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// todo: pass register file directly!
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vm.ByteCode.Interpret(vm)
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vm.reg = vm.ByteCode.Execute(vm.reg, &vm.ScratchPad, vm.config.eMask)
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vm.mem.mx ^= vm.reg.r[vm.config.readReg[2]] ^ vm.reg.r[vm.config.readReg[3]]
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vm.mem.mx &= CacheLineAlignMask
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@ -154,15 +154,15 @@ func (vm *VM) Run(input_hash [64]byte) {
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vm.mem.mx, vm.mem.ma = vm.mem.ma, vm.mem.mx
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for i := uint64(0); i < RegistersCount; i++ {
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binary.LittleEndian.PutUint64(vm.ScratchPad[spAddr1+8*i:], vm.reg.r[i])
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vm.ScratchPad.Store64(uint32(spAddr1+8*i), vm.reg.r[i])
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}
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for i := uint64(0); i < RegistersCountFloat; i++ {
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vm.reg.f[i][LOW] = math.Float64frombits(math.Float64bits(vm.reg.f[i][LOW]) ^ math.Float64bits(vm.reg.e[i][LOW]))
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vm.reg.f[i][HIGH] = math.Float64frombits(math.Float64bits(vm.reg.f[i][HIGH]) ^ math.Float64bits(vm.reg.e[i][HIGH]))
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binary.LittleEndian.PutUint64(vm.ScratchPad[spAddr0+16*i:], math.Float64bits(vm.reg.f[i][LOW]))
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binary.LittleEndian.PutUint64(vm.ScratchPad[spAddr0+16*i+8:], math.Float64bits(vm.reg.f[i][HIGH]))
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vm.ScratchPad.Store64(uint32(spAddr0+16*i), math.Float64bits(vm.reg.f[i][LOW]))
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vm.ScratchPad.Store64(uint32(spAddr0+16*i+8), math.Float64bits(vm.reg.f[i][HIGH]))
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}
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spAddr0 = 0
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@ -173,9 +173,7 @@ func (vm *VM) Run(input_hash [64]byte) {
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}
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func (vm *VM) InitScratchpad(seed *[64]byte) {
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// calculate and fill scratchpad
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clear(vm.ScratchPad[:])
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aes.FillAes1Rx4(seed, vm.ScratchPad[:])
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vm.ScratchPad.Init(seed)
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}
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func (vm *VM) CalculateHash(input []byte, output *[32]byte) {
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@ -30,6 +30,7 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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package randomx
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import (
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"git.gammaspectra.live/P2Pool/go-randomx/v2/aes"
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"unsafe"
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)
|
||||
import "encoding/binary"
|
||||
|
|
@ -76,24 +77,21 @@ func (vm *VM) CompileToBytecode() {
|
|||
switch opcode {
|
||||
case 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15: // 16 frequency
|
||||
ibc.Opcode = VM_IADD_RS
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
if dst != RegisterNeedsDisplacement {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
ibc.shift = (instr.Mod() >> 2) % 4
|
||||
//shift
|
||||
ibc.immB = (instr.Mod() >> 2) % 4
|
||||
ibc.imm = 0
|
||||
} else {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
ibc.shift = (instr.Mod() >> 2) % 4
|
||||
//shift
|
||||
ibc.immB = (instr.Mod() >> 2) % 4
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
||||
case 16, 17, 18, 19, 20, 21, 22: // 7
|
||||
ibc.Opcode = VM_IADD_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -102,26 +100,21 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_IADD_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38: // 16
|
||||
ibc.Opcode = VM_ISUB_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
} else {
|
||||
if src == dst {
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
ibc.isrc = &ibc.imm // we are pointing within bytecode
|
||||
|
||||
ibc.Opcode = VM_ISUB_I
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 39, 40, 41, 42, 43, 44, 45: // 7
|
||||
ibc.Opcode = VM_ISUB_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -130,26 +123,21 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_ISUB_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61: // 16
|
||||
ibc.Opcode = VM_IMUL_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
} else {
|
||||
if src == dst {
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
ibc.isrc = &ibc.imm // we are pointing within bytecode
|
||||
|
||||
ibc.Opcode = VM_IMUL_I
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 62, 63, 64, 65: //4
|
||||
ibc.Opcode = VM_IMUL_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -158,19 +146,16 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_IMUL_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 66, 67, 68, 69: //4
|
||||
ibc.Opcode = VM_IMULH_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
registerUsage[dst] = i
|
||||
case 70: //1
|
||||
ibc.Opcode = VM_IMULH_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -179,19 +164,16 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_IMULH_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 71, 72, 73, 74: //4
|
||||
ibc.Opcode = VM_ISMULH_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
registerUsage[dst] = i
|
||||
case 75: //1
|
||||
ibc.Opcode = VM_ISMULH_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -200,15 +182,14 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_ISMULH_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 76, 77, 78, 79, 80, 81, 82, 83: // 8
|
||||
divisor := instr.IMM()
|
||||
if !isZeroOrPowerOf2(divisor) {
|
||||
ibc.Opcode = VM_IMUL_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.Opcode = VM_IMUL_I
|
||||
ibc.imm = randomx_reciprocal(divisor)
|
||||
ibc.isrc = &ibc.imm
|
||||
registerUsage[dst] = i
|
||||
} else {
|
||||
ibc.Opcode = VM_NOP
|
||||
|
|
@ -216,26 +197,19 @@ func (vm *VM) CompileToBytecode() {
|
|||
|
||||
case 84, 85: //2
|
||||
ibc.Opcode = VM_INEG_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
registerUsage[dst] = i
|
||||
case 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100: //15
|
||||
ibc.Opcode = VM_IXOR_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
} else {
|
||||
if src == dst {
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
ibc.isrc = &ibc.imm // we are pointing within bytecode
|
||||
|
||||
ibc.Opcode = VM_IXOR_I
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 101, 102, 103, 104, 105: //5
|
||||
ibc.Opcode = VM_IXOR_M
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -244,38 +218,28 @@ func (vm *VM) CompileToBytecode() {
|
|||
} else {
|
||||
ibc.Opcode = VM_IXOR_MZ
|
||||
ibc.memMask = ScratchpadL3Mask
|
||||
ibc.imm = uint64(ibc.getScratchpadZeroAddress())
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 106, 107, 108, 109, 110, 111, 112, 113: //8
|
||||
ibc.Opcode = VM_IROR_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
} else {
|
||||
if src == dst {
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
ibc.isrc = &ibc.imm // we are pointing within bytecode
|
||||
|
||||
ibc.Opcode = VM_IROR_I
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
case 114, 115: // 2 IROL_R
|
||||
ibc.Opcode = VM_IROL_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
|
||||
if src != dst {
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
} else {
|
||||
if src == dst {
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
ibc.isrc = &ibc.imm // we are pointing within bytecode
|
||||
|
||||
ibc.Opcode = VM_IROL_I
|
||||
}
|
||||
registerUsage[dst] = i
|
||||
|
||||
case 116, 117, 118, 119: //4
|
||||
if src != dst {
|
||||
ibc.Opcode = VM_ISWAP_R
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
registerUsage[dst] = i
|
||||
registerUsage[src] = i
|
||||
} else {
|
||||
|
|
@ -285,24 +249,21 @@ func (vm *VM) CompileToBytecode() {
|
|||
|
||||
// below are floating point instructions
|
||||
case 120, 121, 122, 123: // 4
|
||||
ibc.Opcode = VM_FSWAP_R
|
||||
//ibc.Opcode = VM_FSWAP_R
|
||||
if dst < RegistersCountFloat {
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.Opcode = VM_FSWAP_RF
|
||||
} else {
|
||||
ibc.fdst = &vm.reg.e[dst-RegistersCountFloat]
|
||||
ibc.Opcode = VM_FSWAP_RE
|
||||
ibc.dst = dst - RegistersCountFloat
|
||||
}
|
||||
case 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139: //16
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.src = instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FADD_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
|
||||
case 140, 141, 142, 143, 144: //5
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FADD_M
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -311,16 +272,12 @@ func (vm *VM) CompileToBytecode() {
|
|||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
|
||||
case 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160: //16
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.src = instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FSUB_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
case 161, 162, 163, 164, 165: //5
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSUB_M
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -329,20 +286,15 @@ func (vm *VM) CompileToBytecode() {
|
|||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
|
||||
case 166, 167, 168, 169, 170, 171: //6
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSCAL_R
|
||||
ibc.fdst = &vm.reg.f[dst]
|
||||
case 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203: //32
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
src := instr.Src() % RegistersCountFloat
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.src = instr.Src() % RegistersCountFloat
|
||||
ibc.Opcode = VM_FMUL_R
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
ibc.fsrc = &vm.reg.a[src]
|
||||
case 204, 205, 206, 207: //4
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FDIV_M
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
ibc.memMask = ScratchpadL1Mask
|
||||
} else {
|
||||
|
|
@ -350,15 +302,17 @@ func (vm *VM) CompileToBytecode() {
|
|||
}
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
case 208, 209, 210, 211, 212, 213: //6
|
||||
dst := instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.dst = instr.Dst() % RegistersCountFloat // bit shift optimization
|
||||
ibc.Opcode = VM_FSQRT_R
|
||||
ibc.fdst = &vm.reg.e[dst]
|
||||
|
||||
case 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238: //25 // CBRANCH and CFROUND are interchanged
|
||||
ibc.Opcode = VM_CBRANCH
|
||||
reg := instr.Dst() % RegistersCount
|
||||
ibc.isrc = &vm.reg.r[reg]
|
||||
ibc.target = int16(registerUsage[reg])
|
||||
ibc.src = instr.Dst() % RegistersCount
|
||||
|
||||
target := uint16(int16(registerUsage[ibc.src]))
|
||||
ibc.dst = uint8(target)
|
||||
ibc.immB = uint8(target >> 8)
|
||||
|
||||
shift := uint64(instr.Mod()>>4) + CONDITIONOFFSET
|
||||
//conditionmask := CONDITIONMASK << shift
|
||||
ibc.imm = signExtend2sCompl(instr.IMM()) | (uint64(1) << shift)
|
||||
|
|
@ -373,13 +327,10 @@ func (vm *VM) CompileToBytecode() {
|
|||
|
||||
case 239: //1
|
||||
ibc.Opcode = VM_CFROUND
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
ibc.imm = uint64(instr.IMM() & 63)
|
||||
|
||||
case 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255: //16
|
||||
ibc.Opcode = VM_ISTORE
|
||||
ibc.idst = &vm.reg.r[dst]
|
||||
ibc.isrc = &vm.reg.r[src]
|
||||
ibc.imm = signExtend2sCompl(instr.IMM())
|
||||
if (instr.Mod() >> 4) < STOREL3CONDITION {
|
||||
if (instr.Mod() % 4) != 0 {
|
||||
|
|
@ -400,19 +351,30 @@ func (vm *VM) CompileToBytecode() {
|
|||
|
||||
}
|
||||
|
||||
func (vm *VM) Load64(addr uint64) uint64 {
|
||||
return *(*uint64)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
type ScratchPad [ScratchpadSize]byte
|
||||
|
||||
func (pad *ScratchPad) Init(seed *[64]byte) {
|
||||
// calculate and fill scratchpad
|
||||
clear(pad[:])
|
||||
aes.FillAes1Rx4(seed, pad[:])
|
||||
}
|
||||
func (vm *VM) Load32(addr uint64) uint32 {
|
||||
return *(*uint32)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
func (pad *ScratchPad) Store64(addr uint32, val uint64) {
|
||||
*(*uint64)(unsafe.Pointer(&pad[addr])) = val
|
||||
//binary.LittleEndian.PutUint64(pad[addr:], val)
|
||||
}
|
||||
func (pad *ScratchPad) Load64(addr uint32) uint64 {
|
||||
return *(*uint64)(unsafe.Pointer(&pad[addr]))
|
||||
}
|
||||
func (pad *ScratchPad) Load32(addr uint32) uint32 {
|
||||
return *(*uint32)(unsafe.Pointer(&pad[addr]))
|
||||
}
|
||||
|
||||
func (vm *VM) Load32F(addr uint64) (lo, hi float64) {
|
||||
a := *(*[2]int32)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
func (pad *ScratchPad) Load32F(addr uint32) (lo, hi float64) {
|
||||
a := *(*[2]int32)(unsafe.Pointer(&pad[addr]))
|
||||
return float64(a[LOW]), float64(a[HIGH])
|
||||
}
|
||||
|
||||
func (vm *VM) Load32FA(addr uint64) [2]float64 {
|
||||
a := *(*[2]int32)(unsafe.Pointer(&vm.ScratchPad[addr]))
|
||||
func (pad *ScratchPad) Load32FA(addr uint32) [2]float64 {
|
||||
a := *(*[2]int32)(unsafe.Pointer(&pad[addr]))
|
||||
return [2]float64{float64(a[LOW]), float64(a[HIGH])}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue