1089 lines
35 KiB
C
Executable file
1089 lines
35 KiB
C
Executable file
/**************************************************************************
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Copyright (c) 2006-2013, Silicom
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Silicom nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#ifndef BP_MOD_H
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#define BP_MOD_H
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#include "bits.h"
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#ifndef KERNEL_VERSION
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#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
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#endif
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#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
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#define msleep(x) do { if(in_interrupt()) { \
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/* Don't mdelay in interrupt context! */ \
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BUG(); \
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} else { \
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set_current_state(TASK_UNINTERRUPTIBLE); \
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schedule_timeout((x * HZ)/1000 + 2); \
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} } while(0)
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#endif
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#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,10))
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#define EXPORT_SYMBOL_NOVERS EXPORT_SYMBOL
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#endif
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#define BP_PROC_DIR "bypass"
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#define GPIO6_SET_ENTRY_SD "gpio6_set"
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#define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
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#define GPIO7_SET_ENTRY_SD "gpio7_set"
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#define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
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#define PULSE_SET_ENTRY_SD "pulse_set"
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#define ZERO_SET_ENTRY_SD "zero_set"
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#define PULSE_GET1_ENTRY_SD "pulse_get1"
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#define PULSE_GET2_ENTRY_SD "pulse_get2"
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#define CMND_ON_ENTRY_SD "cmnd_on"
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#define CMND_OFF_ENTRY_SD "cmnd_off"
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#define RESET_CONT_ENTRY_SD "reset_cont"
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/*COMMANDS*/
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#define BYPASS_INFO_ENTRY_SD "bypass_info"
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#define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
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#define BYPASS_CAPS_ENTRY_SD "bypass_caps"
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#define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
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#define BYPASS_ENTRY_SD "bypass"
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#define BYPASS_CHANGE_ENTRY_SD "bypass_change"
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#define BYPASS_WD_ENTRY_SD "bypass_wd"
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#define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
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#define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
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#define DIS_BYPASS_ENTRY_SD "dis_bypass"
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#define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
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#define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
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#define STD_NIC_ENTRY_SD "std_nic"
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#define STD_NIC_ENTRY_SD "std_nic"
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#define TAP_ENTRY_SD "tap"
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#define TAP_CHANGE_ENTRY_SD "tap_change"
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#define DIS_TAP_ENTRY_SD "dis_tap"
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#define TAP_PWUP_ENTRY_SD "tap_pwup"
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#define TWO_PORT_LINK_ENTRY_SD "two_port_link"
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#define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
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#define WD_AUTORESET_ENTRY_SD "wd_autoreset"
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#define TPL_ENTRY_SD "tpl"
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#define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
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#define HW_RESET_ENTRY_SD "hw_reset"
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#define DISC_ENTRY_SD "disc"
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#define DISC_CHANGE_ENTRY_SD "disc_change"
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#define DIS_DISC_ENTRY_SD "dis_disc"
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#define DISC_PWUP_ENTRY_SD "disc_pwup"
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#ifndef jiffies_to_msecs
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#define jiffies_to_msecs(x) _kc_jiffies_to_msecs(x)
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static inline unsigned int jiffies_to_msecs(const unsigned long j)
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{
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#if HZ <= 1000 && !(1000 % HZ)
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return(1000 / HZ) * j;
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#elif HZ > 1000 && !(HZ % 1000)
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return(j + (HZ / 1000) - 1)/(HZ / 1000);
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#else
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return(j * 1000) / HZ;
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#endif
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}
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#endif
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
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#define pci_get_class pci_find_class
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#define pci_get_subsys pci_find_subsys
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#define pci_get_device pci_find_device
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#endif
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4))
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#define MODULE_VERSION(_version)
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#endif
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#define SILICOM_VID 0x1374
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#define SILICOM_SVID 0x1374
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#define SILICOM_PXG2BPFI_SSID 0x0026
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#define SILICOM_PXG2BPFILX_SSID 0x0027
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#define SILICOM_PXGBPI_SSID 0x0028
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#define SILICOM_PXGBPIG_SSID 0x0029
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#define SILICOM_PXG2TBFI_SSID 0x002a
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#define SILICOM_PXG4BPI_SSID 0x002c
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#define SILICOM_PXG4BPFI_SSID 0x002d
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#define SILICOM_PXG4BPFILX_SSID 0x002e
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#define SILICOM_PXG2BPFIL_SSID 0x002F
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#define SILICOM_PXG2BPFILLX_SSID 0x0030
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#define SILICOM_PEG4BPI_SSID 0x0031
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#define SILICOM_PEG2BPI_SSID 0x0037
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#define SILICOM_PEG4BPIN_SSID 0x0038
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#define SILICOM_PEG2BPFI_SSID 0x0039
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#define SILICOM_PEG2BPFILX_SSID 0x003A
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#define SILICOM_PMCXG2BPFI_SSID 0x003B
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#define NOKIA_PMCXG2BPFIN_SSID 0x0510
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#define NOKIA_PMCXG2BPIN_SSID 0x0513
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#define NOKIA_PMCXG4BPIN_SSID 0x0514
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#define NOKIA_PMCXG2BPFIN_SVID 0x13B8
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#define NOKIA_PMCXG2BPIN2_SSID 0x0515
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#define NOKIA_PMCXG4BPIN2_SSID 0x0516
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#define SILICOM_PMCX2BPI_SSID 0x041
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#define SILICOM_PMCX4BPI_SSID 0x042
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#define SILICOM_PXG2BISC1_SSID 0x003d
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#define SILICOM_PEG2TBFI_SSID 0x003E
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#define SILICOM_PXG2TBI_SSID 0x003f
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#define SILICOM_PXG4BPFID_SSID 0x0043
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#define SILICOM_PEG4BPFI_SSID 0x0040
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#define SILICOM_PEG4BPIPT_SSID 0x0044
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#define SILICOM_PXG6BPI_SSID 0x0045
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#define SILICOM_PEG4BPIL_SSID 0x0046
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#define SILICOM_PEG2BPI5_SSID 0x0052
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#define SILICOM_PEG6BPI_SSID 0x0053
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#define SILICOM_PEG4BPFI5_SSID 0x0050
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#define SILICOM_PEG4BPFI5LX_SSID 0x0051
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#define SILICOM_PEG2BISC6_SSID 0x54
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#define SILICOM_PEG6BPIFC_SSID 0x55
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#define SILICOM_PEG2BPFI5_SSID 0x0056
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#define SILICOM_PEG2BPFI5LX_SSID 0x0057
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#define SILICOM_PXEG4BPFI_SSID 0x0058
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#define SILICOM_PEG2BPFID_SSID 0x0047
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#define SILICOM_PEG2BPFIDLX_SSID 0x004C
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#define SILICOM_MEG2BPFILN_SSID 0x0048
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#define SILICOM_MEG2BPFINX_SSID 0x0049
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#define SILICOM_PEG4BPFILX_SSID 0x004A
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#define SILICOM_MHIO8AD_SSID 0x004F
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#define SILICOM_MEG2BPFILXLN_SSID 0x004b
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#define SILICOM_PEG2BPIX1_SSID 0x004d
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#define SILICOM_MEG2BPFILXNX_SSID 0x004e
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#define SILICOM_PE10G2BPISR_SSID 0x0102
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#define SILICOM_PE10G2BPILR_SSID 0x0103
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#define SILICOM_PE10G2BPICX4_SSID 0x0101
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#define SILICOM_XE10G2BPILR_SSID 0x0163
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#define SILICOM_XE10G2BPISR_SSID 0x0162
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#define SILICOM_XE10G2BPICX4_SSID 0x0161
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#define SILICOM_XE10G2BPIT_SSID 0x0160
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#define SILICOM_PE10GDBISR_SSID 0x0181
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#define SILICOM_PE10GDBILR_SSID 0x0182
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#define SILICOM_PE210G2DBi9SR_SSID 0x0188
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#define SILICOM_PE210G2DBi9SRRB_SSID 0x0188
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#define SILICOM_PE210G2DBi9LR_SSID 0x0189
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#define SILICOM_PE210G2DBi9LRRB_SSID 0x0189
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#define SILICOM_PE310G4DBi940SR_SSID 0x018C
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#define SILICOM_PE310G4DBi940LR_SSID 0x018D
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#define SILICOM_PE310G4DBi940T_SSID 0x018e
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#define SILICOM_PE310G4DBi9T_SSID 0x18e
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#define SILICOM_PE310G4BPi9T_SSID 0x130
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#define SILICOM_PE310G4BPi9SR_SSID 0x132
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#define SILICOM_PE310G4BPi9LR_SSID 0x133
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#define SILICOM_PE310G4BPi9SRD_SSID 0x134
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#define SILICOM_PE310G4BPi9LRD_SSID 0x135
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#define SILICOM_M6E310G4BPi9SR_SSID 0x0492
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#define SILICOM_M6E310G4BPi9LR_SSID 0x0493
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#define NOKIA_XE10G2BPIXR_SVID 0x13B8
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#define NOKIA_XE10G2BPIXR_SSID 0x051C
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#define INTEL_PEG4BPII_PID 0x10A0
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#define INTEL_PEG4BPFII_PID 0x10A1
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#define INTEL_PEG4BPII_SSID 0x11A0
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#define INTEL_PEG4BPFII_SSID 0x11A1
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#define INTEL_PEG4BPIIO_SSID 0x10A0
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#define INTEL_PEG4BPIIO_PID 0x105e
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#define BROADCOM_VID 0x14e4
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#define BROADCOM_PE10G2_PID 0x164e
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#define SILICOM_PE10G2BPTCX4_SSID 0x0141
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#define SILICOM_PE10G2BPTSR_SSID 0x0142
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#define SILICOM_PE10G2BPTLR_SSID 0x0143
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#define SILICOM_PE10G2BPTT_SSID 0x0140
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#define SILICOM_PEG4BPI6_SSID 0x0320
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#define SILICOM_PEG4BPFI6_SSID 0x0321
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#define SILICOM_PEG4BPFI6LX_SSID 0x0322
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#define SILICOM_PEG4BPFI6ZX_SSID 0x0323
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#define SILICOM_PEG2BPI6_SSID 0x0300
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#define SILICOM_PEG2BPFI6_SSID 0x0301
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#define SILICOM_PEG2BPFI6LX_SSID 0x0302
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#define SILICOM_PEG2BPFI6ZX_SSID 0x0303
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#define SILICOM_PEG2BPFI6FLXM_SSID 0x0304
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#define SILICOM_PEG2DBI6_SSID 0x0308
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#define SILICOM_PEG2DBFI6_SSID 0x0309
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#define SILICOM_PEG2DBFI6LX_SSID 0x030A
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#define SILICOM_PEG2DBFI6ZX_SSID 0x030B
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#define SILICOM_MEG2BPI6_SSID 0x0310
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#define SILICOM_XEG2BPI6_SSID 0x0318
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#define SILICOM_PEG4BPI6FC_SSID 0x0328
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#define SILICOM_PEG4BPFI6FC_SSID 0x0329
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#define SILICOM_PEG4BPFI6FCLX_SSID 0x032A
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#define SILICOM_PEG4BPFI6FCZX_SSID 0x032B
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#define SILICOM_PEG6BPI6_SSID 0x0340
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#define SILICOM_PE2G6BPI6_SSID 0x0341
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#define SILICOM_PEG2BPI6SC6_SSID 0x0360
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#define SILICOM_MEG2BPI6_SSID 0x0310
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#define SILICOM_XEG2BPI6_SSID 0x0318
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#define SILICOM_MEG4BPI6_SSID 0x0330
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#define SILICOM_PE2G4BPi80L_SSID 0x0380
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#define SILICOM_M6E2G8BPi80A_SSID 0x0474
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#define SILICOM_PE2G4BPi35_SSID 0x03d8
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#define SILICOM_PE2G4BPFi80_SSID 0x0381
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#define SILICOM_PE2G4BPFi80LX_SSID 0x0382
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#define SILICOM_PE2G4BPFi80ZX_SSID 0x0383
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#define SILICOM_PE2G4BPi80_SSID 0x0388
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#define SILICOM_PE2G2BPi80_SSID 0x0390
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#define SILICOM_PE2G2BPFi80_SSID 0x0391
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#define SILICOM_PE2G2BPFi80LX_SSID 0x0392
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#define SILICOM_PE2G2BPFi80ZX_SSID 0x0393
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#define SILICOM_PE2G4BPi35L_SSID 0x03D0
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#define SILICOM_PE2G4BPFi35_SSID 0x03D1
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#define SILICOM_PE2G4BPFi35CS_SSID 0x0b80
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#define SILICOM_PE2G4BPFi35LX_SSID 0x03D2
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#define SILICOM_PE2G4BPFi35ZX_SSID 0x03D3
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#define SILICOM_M1E2G4BPi35_SSID 0x04D0
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#define SILICOM_M1E2G4BPFi35_SSID 0x04D1
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#define SILICOM_M1E2G4BPFi35LX_SSID 0x04D2
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#define SILICOM_M1E2G4BPFi35ZX_SSID 0x04D3
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#define SILICOM_M1E2G4BPi35JP_SSID 0x1800
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#define SILICOM_M1E2G4BPi35JP1_SSID 0x1801
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#define SILICOM_PE2G2BPi35_SSID 0x03c0
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#define SILICOM_PAC1200BPi35_SSID 0x03cc
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#define SILICOM_PE2G2BPFi35_SSID 0x03C1
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#define SILICOM_PE2G2BPFi35LX_SSID 0x03C2
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#define SILICOM_PE2G2BPFi35ZX_SSID 0x03C3
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#define SILICOM_PE2G6BPi35_SSID 0x03E0
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#define SILICOM_PE2G6BPi35CX_SSID 0x0AA0
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#define INTEL_PE210G2SPI9_SSID 0x00C
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#define SILICOM_M1EG2BPI6_SSID 0x400
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#define SILICOM_M1EG2BPFI6_SSID 0x0401
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#define SILICOM_M1EG2BPFI6LX_SSID 0x0402
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#define SILICOM_M1EG2BPFI6ZX_SSID 0x0403
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#define SILICOM_M1EG4BPI6_SSID 0x0420
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#define SILICOM_M1EG4BPFI6_SSID 0x0421
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#define SILICOM_M1EG4BPFI6LX_SSID 0x0422
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#define SILICOM_M1EG4BPFI6ZX_SSID 0x0423
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#define SILICOM_M1EG6BPI6_SSID 0x0440
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#define SILICOM_M1E2G4BPi80_SSID 0x0460
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#define SILICOM_M1E2G4BPFi80_SSID 0x0461
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#define SILICOM_M1E2G4BPFi80LX_SSID 0x0462
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#define SILICOM_M1E2G4BPFi80ZX_SSID 0x0463
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#define SILICOM_M6E2G8BPi80_SSID 0x0470
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#define SILICOM_PE210G2BPi40_SSID 0x01a0
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#define SILICOM_M1E210G2BPI40T_SSID 0x0480
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#define SILICOM_PE310G4BPi40_SSID 0x01a4
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#define PEG540_IF_SERIES(pid) \
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((pid==SILICOM_PE210G2BPi40_SSID) || \
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(pid==SILICOM_PE310G4BPi40_SSID) || \
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(pid==SILICOM_M1E210G2BPI40T_SSID))
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#define OLD_IF_SERIES(pid) \
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((pid==SILICOM_PXG2BPFI_SSID)|| \
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(pid==SILICOM_PXG2BPFILX_SSID))
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#define P2BPFI_IF_SERIES(pid) \
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((pid==SILICOM_PXG2BPFI_SSID)|| \
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(pid==SILICOM_PXG2BPFILX_SSID)|| \
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(pid==SILICOM_PEG2BPFI_SSID)|| \
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(pid==SILICOM_PEG2BPFID_SSID)|| \
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(pid==SILICOM_PEG2BPFIDLX_SSID)|| \
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(pid==SILICOM_MEG2BPFILN_SSID)|| \
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(pid==SILICOM_MEG2BPFINX_SSID)|| \
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(pid==SILICOM_PEG4BPFILX_SSID)|| \
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(pid==SILICOM_PEG4BPFI_SSID)|| \
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(pid==SILICOM_PXEG4BPFI_SSID)|| \
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(pid==SILICOM_PXG4BPFID_SSID)|| \
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(pid==SILICOM_PEG2TBFI_SSID)|| \
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(pid==SILICOM_PE10G2BPISR_SSID)|| \
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(pid==SILICOM_PE10G2BPILR_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFILX_SSID)|| \
|
|
(pid==SILICOM_PMCXG2BPFI_SSID) || \
|
|
(pid==SILICOM_MHIO8AD_SSID) || \
|
|
(pid==SILICOM_PEG4BPFI5LX_SSID) || \
|
|
(pid==SILICOM_PEG4BPFI5_SSID) || \
|
|
(pid==SILICOM_PEG4BPFI6FC_SSID) || \
|
|
(pid==SILICOM_PEG4BPFI6FCLX_SSID) || \
|
|
(pid==SILICOM_PEG4BPFI6FCZX_SSID) || \
|
|
(pid==NOKIA_PMCXG2BPFIN_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILXLN_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILXNX_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPIT_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPICX4_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPISR_SSID)|| \
|
|
(pid==NOKIA_XE10G2BPIXR_SSID)|| \
|
|
(pid==SILICOM_PE10GDBISR_SSID)|| \
|
|
(pid==SILICOM_PE10GDBILR_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPILR_SSID))
|
|
|
|
|
|
#define INTEL_IF_SERIES(pid) \
|
|
((pid==INTEL_PEG4BPII_SSID)|| \
|
|
(pid==INTEL_PEG4BPIIO_SSID)|| \
|
|
(pid==INTEL_PEG4BPFII_SSID))
|
|
|
|
#define NOKIA_SERIES(pid) \
|
|
((pid==NOKIA_PMCXG2BPIN_SSID)|| \
|
|
(pid==NOKIA_PMCXG4BPIN_SSID)|| \
|
|
(pid==SILICOM_PMCX4BPI_SSID)|| \
|
|
(pid==NOKIA_PMCXG2BPFIN_SSID)|| \
|
|
(pid==SILICOM_PMCXG2BPFI_SSID)|| \
|
|
(pid==NOKIA_PMCXG2BPIN2_SSID)|| \
|
|
(pid==NOKIA_PMCXG4BPIN2_SSID)|| \
|
|
(pid==SILICOM_PMCX2BPI_SSID))
|
|
|
|
#define DISCF_IF_SERIES(pid) \
|
|
(pid==SILICOM_PEG2TBFI_SSID)
|
|
|
|
#define PEGF_IF_SERIES(pid) \
|
|
((pid==SILICOM_PEG2BPFI_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFID_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFIDLX_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFILX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI_SSID)|| \
|
|
(pid==SILICOM_PXEG4BPFI_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILN_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFINX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFILX_SSID)|| \
|
|
(pid==SILICOM_PEG2TBFI_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILXLN_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILXNX_SSID))
|
|
|
|
|
|
#define TPL_IF_SERIES(pid) \
|
|
((pid==SILICOM_PXG2BPFIL_SSID)|| \
|
|
(pid==SILICOM_PXG2BPFILLX_SSID)|| \
|
|
(pid==SILICOM_PXG2TBFI_SSID)|| \
|
|
(pid==SILICOM_PXG4BPFID_SSID)|| \
|
|
(pid==SILICOM_PXG4BPFI_SSID))
|
|
|
|
|
|
#define BP10G_IF_SERIES(pid) \
|
|
((pid==SILICOM_PE10G2BPISR_SSID)|| \
|
|
(pid==SILICOM_PE10G2BPICX4_SSID)|| \
|
|
(pid==SILICOM_PE10G2BPILR_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPIT_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPICX4_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPISR_SSID)|| \
|
|
(pid==NOKIA_XE10G2BPIXR_SSID)|| \
|
|
(pid==SILICOM_PE10GDBISR_SSID)|| \
|
|
(pid==SILICOM_PE10GDBILR_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPILR_SSID))
|
|
|
|
#define BP10GB_IF_SERIES(pid) \
|
|
((pid==SILICOM_PE10G2BPTCX4_SSID)|| \
|
|
(pid==SILICOM_PE10G2BPTSR_SSID)|| \
|
|
(pid==SILICOM_PE10G2BPTLR_SSID)|| \
|
|
(pid==SILICOM_PE10G2BPTT_SSID))
|
|
|
|
|
|
|
|
#define BP10G_CX4_SERIES(pid) \
|
|
(pid==SILICOM_PE10G2BPICX4_SSID)
|
|
|
|
#define BP10GB_CX4_SERIES(pid) \
|
|
(pid==SILICOM_PE10G2BPTCX4_SSID)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define SILICOM_M2EG2BPFI6_SSID 0x0401
|
|
#define SILICOM_M2EG2BPFI6LX_SSID 0x0402
|
|
#define SILICOM_M2EG2BPFI6ZX_SSID 0x0403
|
|
#define SILICOM_M2EG4BPI6_SSID 0x0420
|
|
|
|
#define SILICOM_M2EG4BPFI6_SSID 0x0421
|
|
#define SILICOM_M2EG4BPFI6LX_SSID 0x0422
|
|
#define SILICOM_M2EG4BPFI6ZX_SSID 0x0423
|
|
|
|
#define SILICOM_M2EG6BPI6_SSID 0x0440
|
|
|
|
|
|
|
|
|
|
|
|
#define SILICOM_M1E10G2BPI9CX4_SSID 0x481
|
|
#define SILICOM_M1E10G2BPI9SR_SSID 0x482
|
|
#define SILICOM_M1E10G2BPI9LR_SSID 0x483
|
|
//#define SILICOM_M1E10G2BPI9T_SSID 0x480
|
|
|
|
#define SILICOM_M2E10G2BPI9CX4_SSID 0x481
|
|
#define SILICOM_M2E10G2BPI9SR_SSID 0x482
|
|
#define SILICOM_M2E10G2BPI9LR_SSID 0x483
|
|
#define SILICOM_M2E10G2BPI9T_SSID 0x480
|
|
|
|
|
|
#define SILICOM_PE210G2BPI9CX4_SSID 0x121
|
|
#define SILICOM_PE210G2BPI9SR_SSID 0x122
|
|
#define SILICOM_PE210G2BPI9LR_SSID 0x123
|
|
#define SILICOM_PE210G2BPI9LRD_SSID 0x125
|
|
#define SILICOM_PE210G2BPI9SRD_SSID 0x124
|
|
#define SILICOM_PE210G2BPI9T_SSID 0x120
|
|
|
|
#define SILICOM_M1E210G2BPI9SRDJP_SSID 0x1E00
|
|
#define SILICOM_M1E210G2BPI9SRDJP1_SSID 0x1E10
|
|
#define SILICOM_M1E210G2BPI9LRDJP_SSID 0x1F00
|
|
#define SILICOM_M1E210G2BPI9LRDJP1_SSID 0x1F10
|
|
|
|
#define SILICOM_PE310G4BPI71SRD_SSID 0x0502
|
|
#define SILICOM_PE310G4BPI71LRD_SSID 0x0503
|
|
#define SILICOM_PE340G2BPI71QS4_SSID 0x0512
|
|
#define SILICOM_PE340G2BPI71QL4_SSID 0x0513
|
|
|
|
|
|
#define BP40_IF_SERIES(pid) \
|
|
((pid==SILICOM_PE310G4BPI71SRD_SSID)|| \
|
|
(pid== SILICOM_PE310G4BPI71LRD_SSID)|| \
|
|
(pid==SILICOM_PE340G2BPI71QS4_SSID)|| \
|
|
(pid==SILICOM_PE340G2BPI71QL4_SSID))
|
|
|
|
|
|
#define DBI_IF_SERIES(pid) \
|
|
((pid==SILICOM_PE10GDBISR_SSID)|| \
|
|
(pid==SILICOM_PE10GDBILR_SSID)|| \
|
|
(pid==SILICOM_XE10G2BPILR_SSID)|| \
|
|
(pid==SILICOM_PE210G2DBi9LR_SSID))
|
|
|
|
|
|
#define PEGF5_IF_SERIES(pid) \
|
|
((pid==SILICOM_PEG2BPFI5_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFI5LX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI6_SSID)|| \
|
|
(pid==SILICOM_PE2G6BPI6_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFI6_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFI6FLXM_SSID)|| \
|
|
(pid==SILICOM_PEG2DBFI6_SSID)|| \
|
|
(pid==SILICOM_PEG2DBFI6LX_SSID)|| \
|
|
(pid==SILICOM_PEG2DBFI6ZX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPI6FC_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI6FCLX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPI6FC_SSID)|| \
|
|
(pid==SILICOM_M1EG2BPFI6_SSID)|| \
|
|
(pid==SILICOM_M1EG2BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_M1EG2BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_M1EG4BPFI6_SSID)|| \
|
|
(pid==SILICOM_M1EG4BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_M1EG4BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_M2EG2BPFI6_SSID)|| \
|
|
(pid==SILICOM_M2EG2BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_M2EG2BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_M2EG4BPFI6_SSID)|| \
|
|
(pid==SILICOM_M2EG4BPFI6LX_SSID)|| \
|
|
(pid==SILICOM_M2EG4BPFI6ZX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI6FCZX_SSID))
|
|
|
|
|
|
|
|
|
|
#define PEG5_IF_SERIES(pid) \
|
|
((pid==SILICOM_PEG4BPI6_SSID)|| \
|
|
(pid==SILICOM_PEG2BPI6_SSID)|| \
|
|
(pid==SILICOM_PEG2BPI6SC6_SSID)|| \
|
|
(pid==SILICOM_PEG4BPI6FC_SSID)|| \
|
|
(pid==SILICOM_PEG6BPI6_SSID)|| \
|
|
(pid==SILICOM_MEG2BPI6_SSID)|| \
|
|
(pid==SILICOM_XEG2BPI6_SSID)|| \
|
|
(pid==SILICOM_MEG4BPI6_SSID)|| \
|
|
(pid==SILICOM_M1EG2BPI6_SSID)|| \
|
|
(pid==SILICOM_M1EG4BPI6_SSID)|| \
|
|
(pid==SILICOM_M1EG6BPI6_SSID)|| \
|
|
(pid==SILICOM_PEG6BPI_SSID)|| \
|
|
(pid==SILICOM_PEG4BPIL_SSID)|| \
|
|
(pid==SILICOM_PEG2BISC6_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPi35_SSID)|| \
|
|
(pid==SILICOM_PAC1200BPi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi35L_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35JP_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35JP1_SSID)|| \
|
|
(pid==SILICOM_PE2G6BPi35_SSID)|| \
|
|
(pid==SILICOM_PEG2BPI5_SSID))
|
|
|
|
|
|
#define PEG80_IF_SERIES(pid) \
|
|
((pid==SILICOM_M1E2G4BPi80_SSID)|| \
|
|
(pid==SILICOM_M6E2G8BPi80_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi80L_SSID)|| \
|
|
(pid==SILICOM_M6E2G8BPi80A_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPi35_SSID)|| \
|
|
(pid==SILICOM_PAC1200BPi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi35L_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35JP_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPi35JP1_SSID)|| \
|
|
(pid==SILICOM_PE2G6BPi35_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPi80_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPi80_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80LX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80LX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35ZX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35CS_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35ZX_SSID))
|
|
|
|
|
|
#define PEGF80_IF_SERIES(pid) \
|
|
((pid==SILICOM_PE2G4BPFi80_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80LX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi80_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi80LX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80LX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi80ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_PE2G2BPFi35ZX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_M1E2G4BPFi35ZX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35CS_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35LX_SSID)|| \
|
|
(pid==SILICOM_PE2G4BPFi35ZX_SSID))
|
|
|
|
|
|
#define BP10G9_IF_SERIES(pid) \
|
|
((pid==INTEL_PE210G2SPI9_SSID)|| \
|
|
(pid==SILICOM_M1E10G2BPI9CX4_SSID)|| \
|
|
(pid==SILICOM_M1E10G2BPI9SR_SSID)|| \
|
|
(pid==SILICOM_M1E10G2BPI9LR_SSID)|| \
|
|
(pid==SILICOM_M2E10G2BPI9CX4_SSID)|| \
|
|
(pid==SILICOM_M2E10G2BPI9SR_SSID)|| \
|
|
(pid==SILICOM_M2E10G2BPI9LR_SSID)|| \
|
|
(pid==SILICOM_M2E10G2BPI9T_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9CX4_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9SR_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9LR_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9LRD_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9SRD_SSID)|| \
|
|
(pid==SILICOM_PE210G2DBi9SR_SSID)|| \
|
|
(pid==SILICOM_PE210G2DBi9SRRB_SSID)|| \
|
|
(pid==SILICOM_PE210G2DBi9LR_SSID)|| \
|
|
(pid==SILICOM_PE210G2DBi9LRRB_SSID)|| \
|
|
(pid==SILICOM_PE310G4DBi940SR_SSID)|| \
|
|
(pid==SILICOM_PE310G4DBi940LR_SSID)|| \
|
|
(pid==SILICOM_PE310G4DBi940T_SSID)|| \
|
|
(pid==SILICOM_PE310G4DBi9T_SSID)|| \
|
|
(pid==SILICOM_PE310G4BPi9T_SSID)|| \
|
|
(pid==SILICOM_PE310G4BPi9SR_SSID)|| \
|
|
(pid==SILICOM_PE310G4BPi9SRD_SSID)|| \
|
|
(pid==SILICOM_M6E310G4BPi9SR_SSID)|| \
|
|
(pid==SILICOM_M6E310G4BPi9LR_SSID)|| \
|
|
(pid==SILICOM_PE310G4BPi9LR_SSID)|| \
|
|
(pid==SILICOM_PE310G4BPi9LRD_SSID)|| \
|
|
(pid==SILICOM_M1E210G2BPI9SRDJP_SSID)|| \
|
|
(pid==SILICOM_M1E210G2BPI9SRDJP1_SSID)|| \
|
|
(pid==SILICOM_M1E210G2BPI9LRDJP_SSID)|| \
|
|
(pid==SILICOM_M1E210G2BPI9LRDJP1_SSID)|| \
|
|
(pid==SILICOM_PE210G2BPI9T_SSID))
|
|
|
|
#define BP71_IF_SERIES(pid) \
|
|
((pid==SILICOM_PEG2BPI_SSID)|| \
|
|
(pid==SILICOM_PEG2BPIX1_SSID)|| \
|
|
(pid==SILICOM_PEG4BPIN_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFILX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFI_SSID)|| \
|
|
(pid==SILICOM_PEG2TBFI_SSID)|| \
|
|
(pid==SILICOM_PEG4BPIPT_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFID_SSID)|| \
|
|
(pid==SILICOM_PEG2BPFIDLX_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILN_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFINX_SSID)|| \
|
|
(pid==SILICOM_PEG4BPFILX_SSID)|| \
|
|
(pid==SILICOM_MEG2BPFILXLN_SSID)||\
|
|
(pid==SILICOM_PXEG4BPFI_SSID))
|
|
|
|
|
|
|
|
|
|
/*******************************************************/
|
|
/* 1G INTERFACE ****************************************/
|
|
/*******************************************************/
|
|
|
|
/* Intel Registers */
|
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#define BPCTLI_CTRL 0x00000
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#define BPCTLI_LEDCTL 0x00E00
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#define BPCTLI_CTRL_SWDPIO0 0x00400000
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#define BPCTLI_CTRL_SWDPIN0 0x00040000
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#define BPCTLI_DCA_ID 0x5B70
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#define BPCTLI_CTRL_EXT 0x00018 /* Extended Device Control - RW */
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#define BPCTLI_STATUS 0x00008 /* Device Status - RO */
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#define BPCTLI_EERD 0x14
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#define BPCTLI_EEWR 0x102c
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/* HW related */
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#define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
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#define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
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#define BPCTLI_CTRL_SDP0_DATA 0x00040000 /* SWDPIN 0 value */
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#define BPCTLI_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
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#define BPCTLI_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
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#define BPCTLI_CTRL_SDP0_DIR 0x00400000 /* SDP0 Input or output */
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#define BPCTLI_CTRL_SWDPIN0 0x00040000
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#define BPCTLI_CTRL_SWDPIN1 0x00080000
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#define BPCTLI_CTRL_SDP1_DIR 0x00800000
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#define BPCTLI_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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#define BPCTLI_CTRL_SDP0_SHIFT 18
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#define BPCTLI_CTRL_EXT_SDP6_SHIFT 6
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#define BPCTLI_STATUS_TBIMODE 0x00000020
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#define BPCTLI_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
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#define BPCTLI_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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#define BPCTLI_LEDCTL_MODE_LED_ON 0xE
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#define BPCTLI_LEDCTL_MODE_LED_OFF 0xF
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#define BPCTLI_LEDCTL_LED0_MODE_MASK 0x0000000F
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#define BPCTLI_LEDCTL_LED0_MODE_SHIFT 0
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#define BPCTLI_LEDCTL_LED0_BLINK_RATE 0x0000020
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#define BPCTLI_LEDCTL_LED0_IVRT 0x00000040
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#define BPCTLI_LEDCTL_LED0_BLINK 0x00000080
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#define BPCTLI_CTRL_EXT_MCLK_DIR BPCTLI_CTRL_EXT_SDP7_DIR
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#define BPCTLI_CTRL_EXT_MCLK_DATA BPCTLI_CTRL_EXT_SDP7_DATA
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#define BPCTLI_CTRL_EXT_MDIO_DIR BPCTLI_CTRL_EXT_SDP6_DIR
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#define BPCTLI_CTRL_EXT_MDIO_DATA BPCTLI_CTRL_EXT_SDP6_DATA
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#define BPCTLI_CTRL_EXT_MCLK_DIR5 BPCTLI_CTRL_SDP1_DIR
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#define BPCTLI_CTRL_EXT_MCLK_DATA5 BPCTLI_CTRL_SWDPIN1
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#define BPCTLI_CTRL_EXT_MCLK_DIR80 BPCTLI_CTRL_EXT_SDP6_DIR
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#define BPCTLI_CTRL_EXT_MCLK_DATA80 BPCTLI_CTRL_EXT_SDP6_DATA
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#define BPCTLI_CTRL_EXT_MDIO_DIR5 BPCTLI_CTRL_SWDPIO0
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#define BPCTLI_CTRL_EXT_MDIO_DATA5 BPCTLI_CTRL_SWDPIN0
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#define BPCTLI_CTRL_EXT_MDIO_DIR80 BPCTLI_CTRL_SWDPIO0
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#define BPCTLI_CTRL_EXT_MDIO_DATA80 BPCTLI_CTRL_SWDPIN0
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#define BPCTL_WRITE_REG(a, reg, value) \
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(writel((value), (void *)(((a)->mem_map) + BPCTLI_##reg)))
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#define BPCTL_READ_REG(a, reg) ( \
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readl((void *)((a)->mem_map) + BPCTLI_##reg))
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#define BPCTL_WRITE_FLUSH(a) BPCTL_READ_REG(a, STATUS)
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#define BPCTL_BP_WRITE_REG(a, reg, value) ({ \
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BPCTL_WRITE_REG(a, reg, value); \
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BPCTL_WRITE_FLUSH(a);})
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/**************************************************************/
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/************** 82575 Interface********************************/
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/**************************************************************/
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#define BPCTLI_MII_CR_POWER_DOWN 0x0800
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#define BPCTLI_PHY_CONTROL 0x00 /* Control Register */
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#define BPCTLI_MDIC 0x00020 /* MDI Control - RW */
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#define BPCTLI_IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
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#define BPCTLI_MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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#define BPCTLI_MDIC_DATA_MASK 0x0000FFFF
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#define BPCTLI_MDIC_REG_MASK 0x001F0000
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#define BPCTLI_MDIC_REG_SHIFT 16
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#define BPCTLI_MDIC_PHY_MASK 0x03E00000
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#define BPCTLI_MDIC_PHY_SHIFT 21
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#define BPCTLI_MDIC_OP_WRITE 0x04000000
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#define BPCTLI_MDIC_OP_READ 0x08000000
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#define BPCTLI_MDIC_READY 0x10000000
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#define BPCTLI_MDIC_INT_EN 0x20000000
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#define BPCTLI_MDIC_ERROR 0x40000000
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#define BPCTLI_SWFW_PHY0_SM 0x02
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#define BPCTLI_SWFW_PHY1_SM 0x04
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#define BPCTLI_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
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#define BPCTLI_SWSM 0x05B50 /* SW Semaphore */
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#define BPCTLI_FWSM 0x05B54 /* FW Semaphore */
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#define BPCTLI_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
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#define BPCTLI_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
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#define BPCTLI_MAX_PHY_MULTI_PAGE_REG 0xF
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#define BPCTLI_GEN_POLL_TIMEOUT 640
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/********************************************************/
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/********************************************************/
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/* 10G INTERFACE ****************************************/
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/********************************************************/
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#define BP10G_I2CCTL 0x28
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/* I2CCTL Bit Masks */
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#define BP10G_I2C_CLK_IN 0x00000001
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#define BP10G_I2C_CLK_OUT 0x00000002
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#define BP10G_I2C_DATA_IN 0x00000004
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#define BP10G_I2C_DATA_OUT 0x00000008
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#define BP10G_ESDP 0x20
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#define BP10G_DCA_ID 0x11070
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#define BP10G_SDP0_DIR 0x100
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#define BP10G_SDP1_DIR 0x200
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#define BP10G_SDP3_DIR 0x800
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#define BP10G_SDP4_DIR BIT_12
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#define BP10G_SDP5_DIR 0x2000
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#define BP10G_SDP0_DATA 0x001
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#define BP10G_SDP1_DATA 0x002
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#define BP10G_SDP3_DATA 0x008
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#define BP10G_SDP4_DATA 0x010
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#define BP10G_SDP5_DATA 0x020
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#define BP10G_SDP2_DIR 0x400
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#define BP10G_SDP2_DATA 0x4
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#define BP10G_EODSDP 0x28
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#define BP10G_SDP6_DATA_IN 0x001
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#define BP10G_SDP6_DATA_OUT 0x002
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#define BP10G_SDP7_DATA_IN 0x004
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#define BP10G_SDP7_DATA_OUT 0x008
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#define BP10G_MCLK_DATA_OUT BP10G_SDP7_DATA_OUT
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#define BP10G_MDIO_DATA_OUT BP10G_SDP6_DATA_OUT
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#define BP10G_MDIO_DATA_IN BP10G_SDP6_DATA_IN
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#define BP10G_MDIO_DATA /*BP10G_SDP5_DATA*/ BP10G_SDP3_DATA
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#define BP10G_MDIO_DIR /*BP10G_SDP5_DIR*/ BP10G_SDP3_DATA
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/*#define BP10G_MCLK_DATA_OUT9 BP10G_I2C_CLK_OUT
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#define BP10G_MDIO_DATA_OUT9 BP10G_I2C_DATA_OUT*/
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/*#define BP10G_MCLK_DATA_OUT9*/ /*BP10G_I2C_DATA_OUT*/
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#define BP10G_MDIO_DATA_OUT9 BP10G_I2C_DATA_OUT /*BP10G_I2C_CLK_OUT*/
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/* VIA EOSDP ! */
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#define BP10G_MCLK_DATA_OUT9 BP10G_SDP4_DATA
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#define BP10G_MCLK_DIR_OUT9 BP10G_SDP4_DIR
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/*#define BP10G_MDIO_DATA_IN9 BP10G_I2C_DATA_IN*/
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#define BP10G_MDIO_DATA_IN9 BP10G_I2C_DATA_IN /*BP10G_I2C_CLK_IN*/
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#define BP10G_LEDCTL 0x00200
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/* LEDCTL Bit Masks */
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#define BP10G_LED_IVRT_BASE 0x00000040
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#define BP10G_LED_BLINK_BASE 0x00000080
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#define BP10G_LED_MODE_MASK_BASE 0x0000000F
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#define BP10G_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
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#define BP10G_LED_MODE_SHIFT(_i) (8*(_i))
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#define BP10G_LED_IVRT(_i) BP10G_LED_OFFSET(BP10G_LED_IVRT_BASE, _i)
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#define BP10G_LED_BLINK(_i) BP10G_LED_OFFSET(BP10G_LED_BLINK_BASE, _i)
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#define BP10G_LED_MODE_MASK(_i) BP10G_LED_OFFSET(BP10G_LED_MODE_MASK_BASE, _i)
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/* LED modes */
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#define BP10G_LED_LINK_UP 0x0
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#define BP10G_LED_LINK_10G 0x1
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#define BP10G_LED_MAC 0x2
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#define BP10G_LED_FILTER 0x3
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#define BP10G_LED_LINK_ACTIVE 0x4
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#define BP10G_LED_LINK_1G 0x5
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#define BP10G_LED_ON 0xE
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#define BP10G_LED_OFF 0xF
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#define BP10G_STATUS 0x00008
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#define BP540_MDIO_DATA /*BP10G_SDP5_DATA*/ BP10G_SDP0_DATA
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#define BP540_MDIO_DIR /*BP10G_SDP5_DIR*/ BP10G_SDP0_DIR
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#define BP540_MCLK_DATA BP10G_SDP2_DATA
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#define BP540_MCLK_DIR BP10G_SDP2_DIR
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#define BP10G_WRITE_REG(a, reg, value) \
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(writel((value), (void *)(((a)->mem_map) + BP10G_##reg)))
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#define BP10G_READ_REG(a, reg) ( \
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readl((void *)((a)->mem_map) + BP10G_##reg))
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/*****BROADCOM*******************************************/
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#define BP10GB_MISC_REG_GPIO 0xa490
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#define BP10GB_GPIO3_P0 BIT_3
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#define BP10GB_GPIO3_P1 BIT_7
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#define BP10GB_GPIO3_SET_P0 BIT_11
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#define BP10GB_GPIO3_CLR_P0 BIT_19
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#define BP10GB_GPIO3_OE_P0 BIT_27
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#define BP10GB_GPIO3_SET_P1 BIT_15
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#define BP10GB_GPIO3_CLR_P1 BIT_23
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#define BP10GB_GPIO3_OE_P1 BIT_31
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#define BP10GB_GPIO0_P1 0x10
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#define BP10GB_GPIO0_P0 0x1
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#define BP10GB_GPIO0_CLR_P0 0x10000
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#define BP10GB_GPIO0_CLR_P1 0x100000
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#define BP10GB_GPIO0_SET_P0 0x100
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#define BP10GB_GPIO0_SET_P1 0x1000
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#define BP10GB_GPIO0_OE_P1 0x10000000
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#define BP10GB_GPIO0_OE_P0 0x1000000
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#define BP10GB_MISC_REG_SPIO 0xa4fc
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#define BP10GB_GPIO4_OE BIT_28
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#define BP10GB_GPIO5_OE BIT_29
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#define BP10GB_GPIO4_CLR BIT_20
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#define BP10GB_GPIO5_CLR BIT_21
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#define BP10GB_GPIO4_SET BIT_12
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#define BP10GB_GPIO5_SET BIT_13
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#define BP10GB_GPIO4 BIT_4
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#define BP10GB_GPIO5 BIT_5
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#define BP10GB_MCLK_DIR BP10GB_GPIO5_OE
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#define BP10GB_MDIO_DIR BP10GB_GPIO4_OE
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#define BP10GB_MCLK_DATA BP10GB_GPIO5
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#define BP10GB_MDIO_DATA BP10GB_GPIO4
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#define BP10GB_MCLK_SET BP10GB_GPIO5_SET
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#define BP10GB_MDIO_SET BP10GB_GPIO4_SET
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#define BP10GB_MCLK_CLR BP10GB_GPIO5_CLR
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#define BP10GB_MDIO_CLR BP10GB_GPIO4_CLR
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/* toggle LED 4 times per second = 2 "blinks" per second */
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#define BPVM_ID_INTERVAL (HZ/4)
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/* bit defines for adapter->led_status */
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#define BPVM_LED_ON 0
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/*#define BPCTLI_LEDCTL_MODE_LED_ON 0xE
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#define BPCTLI_LEDCTL_MODE_LED_OFF 0xF*/
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#define BPCTLI_EEPROM_ID_LED_SETTINGS 0x0004
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#define ID_LED_RESERVED_0000 0x0000
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#define ID_LED_RESERVED_FFFF 0xFFFF
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#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
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(ID_LED_OFF1_OFF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_DEF1_DEF2))
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#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_DEF1_OFF2 << 8) | \
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(ID_LED_DEF1_ON2 << 4) | \
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(ID_LED_DEF1_DEF2))
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#define ID_LED_DEF1_DEF2 0x1
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#define ID_LED_DEF1_ON2 0x2
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#define ID_LED_DEF1_OFF2 0x3
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#define ID_LED_ON1_DEF2 0x4
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#define ID_LED_ON1_ON2 0x5
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#define ID_LED_ON1_OFF2 0x6
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#define ID_LED_OFF1_DEF2 0x7
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#define ID_LED_OFF1_ON2 0x8
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#define ID_LED_OFF1_OFF2 0x9
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#define BPCTL_SUCCESS 0
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#define BPCTL_NVM_POLL_READ 0
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#define BPCTL_NVM_RW_ADDR_SHIFT 2
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#define BPCTL_ERR_NVM 1
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#define BPCTL_NVM_RW_REG_DATA 16
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#define BPCTL_NVM_RW_REG_DONE 2
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#define BPCTL_NVM_RW_REG_START 1
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#define BP40G_I2CCMD 0x000881E0
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#define BP40G_I2CSEL 0x000881C0
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#define BP40G_I2CPARAMS 0x000881AC
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#define BP40G_CLK_DATA_OUT BIT_9
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#define BP40G_MDIO_DATA_OUT BIT_10
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#define BP40G_MDIO_DIR_OUTN BIT_11
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#define BP40G_MDIO_DATA_IN BIT_12
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#define BP40G_CLK_DIR_OUTN BIT_13
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#define BP40G_GPIO_SET 0x00088184
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#define BP40G_GPIO_STAT 0x0008817C
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#define BP40GB_GPIO_OE BIT_4
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#define BP40GB_GPIO_SDP_MODE_MASK (BIT_7 | BIT_8 | BIT_9)
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#define TIME_CLK 10 //40 //20 //10
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#define TIME_DET //10 // 5
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#define BP10GB_WRITE_REG(a, reg, value) \
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(writel((value), (void *)(((a)->mem_map) + BP10GB_##reg)))
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#define BP10GB_READ_REG(a, reg) ( \
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readl((void *)((a)->mem_map) + BP10GB_##reg))
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#define BP10G_WRITE_FLUSH(a) BP10G_READ_REG(a, STATUS)
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#define BP40G_READ_REG(a, reg) ( \
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readl((void *)((a)->mem_map) + BP40G_##reg+0x4*((a)->func)))
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#define BP40G_WRITE_REG(a, reg, value) \
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(writel((value), (void *)(((a)->mem_map) + BP40G_##reg+0x4*((a)->func))))
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#define BP40G_READ_GPIO_CTL(a, n) ( \
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readl((void *)((a)->mem_map) + 0x88100+0x4*n))
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#define BP40G_WRITE_GPIO_CTL(a, n, value) \
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(writel((value), (void *)(((a)->mem_map) + 0x88100+0x4*n)))
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#define BP40G_WR_REG(a, reg, value) \
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(writel((value), (void *)(((a)->mem_map) + BP40G_##reg)))
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#define BP40G_RD_REG(a, reg) ( \
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readl((void *)((a)->mem_map) + BP40G_##reg))
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#endif
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