Upstream release 3.0.5.3

This commit is contained in:
Silicom Ltd 2016-04-09 14:24:46 +00:00 committed by WeebDataHoarder
commit cb2e20770c
15 changed files with 5580 additions and 0 deletions

7
clean Executable file
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#! /bin/sh
BUILD=`pwd`
cd $BUILD/lib
make clean
cd $BUILD/util
make clean

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driver/64/libFocalpointSDK.so Executable file

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driver/64/libLTStdPlatform.so Executable file

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driver/64/rdifd Executable file

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driver/Makefile Executable file
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###########################################################################
PRDPATH_UTIL=/bin
ARCH := $(shell uname -m | sed 's/i.86/i386/')
ifeq ($(ARCH),x86_64)
en64 = 1
endif
ifeq ($(ARCH),ppc64)
en64 = 1
endif
###########################################################################
# Build rules
install:
mkdir -p $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
install rdif $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
mkdir -p /etc/rdi
install -m 444 fm_platform_attributes.cfg /etc/rdi
ifeq (,$(en64))
install ./32/rdifd $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
install ./32/libFocalpointSDK.so $(INSTALL_MOD_PATH)/lib
install ./32/libLTStdPlatform.so $(INSTALL_MOD_PATH)/lib
else
install ./64/rdifd $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
install ./64/libFocalpointSDK.so $(INSTALL_MOD_PATH)/lib
install ./64/libLTStdPlatform.so $(INSTALL_MOD_PATH)/lib
install ./64/libFocalpointSDK.so $(INSTALL_MOD_PATH)/lib64
install ./64/libLTStdPlatform.so $(INSTALL_MOD_PATH)/lib64
endif

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driver/fm_platform_attributes.cfg Executable file
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###########################################################
# Global configurations
###########################################################
#=========================================================#
#Debug configuration flag
#Optional Configuration. Default is NONE.
# CONFIG, MOD_STATE, MOD_INTR, MOD_TYPE, PLAT_LOG
# Use comma delimited for multiple entries, no spaces.
# api.platform.config.debug text CONFIG
#=========================================================#
# Total number of switches in the system
# Required configuration.
api.platform.config.numSwitches int 1
api.platform.config.switch.0.uioDevName text /dev/uio0
#=========================================================#
# Platform name
# Optional Configuration. Default is libertyTrail.
api.platform.config.platformName text rubyRapid
#=========================================================#
# Interrupt parameters
api.platform.config.switch.0.msiEnabled bool true
#####################################################################
# Switch configurations
#####################################################################
#===================================================================#
# Switch number for the specified switch index
# Note switch index is also the same as API sw argument.
# Switch number is the value that will be passed down to the shared
# library interfaces as well as kernel module driver interfaces.
# Optional configuration.
# If not specified then switch number is the same as switch index.
api.platform.config.switch.0.switchNumber int 0
#===================================================================#
# LED polling period, for software driven LED
# See SW_LED in port capabilities.
#optional configuration. Default 500 msec.
api.platform.config.switch.0.ledPollPeriodMsec int 200
api.platform.config.switch.0.ledBlinkMode text HW_ASSISTED
api.platform.config.switch.0.portIntrGpio int 6
api.platform.config.switch.0.i2cResetGpio int 5
#===================================================================#
#Transceiver management polling period
#optional configuration. Default 1000 msec.
#api.platform.config.switch.0.xcvrPollPeriodMsec int 0
#===================================================================#
# Total number of ports on the switch, including CPU port
# Required configuration
# This is the number of portIndex below
api.platform.config.switch.0.numPorts int 5
###############################################################################
# Port configurations
###############################################################################
# For receiving/transmitting packets to/from API using raw socket
# Changing pep number also requires swapping associated PCIE portMapping entries
#api.platform.config.switch.0.netDevName text p1p3
api.platform.config.switch.0.cpuPort int 4
api.platform.config.switch.0.bootCfg.mgmtPep int 2
# CPU port (PEP #8 --> PCIE x1)
api.platform.config.switch.0.portIndex.0.portMapping text "LOG=0 PCIE=8"
# SFPP
# QSFP0
api.platform.config.switch.0.portIndex.1.lane.0.portMapping text "LOG=1 EPL=0 LANE=0"
api.platform.config.switch.0.portIndex.1.lane.1.portMapping text "LOG=1 EPL=0 LANE=1"
api.platform.config.switch.0.portIndex.1.lane.2.portMapping text "LOG=1 EPL=0 LANE=2"
api.platform.config.switch.0.portIndex.1.lane.3.portMapping text "LOG=1 EPL=0 LANE=3"
# QSFP1 (with different lane ordering)
api.platform.config.switch.0.portIndex.2.lane.0.portMapping text "LOG=2 EPL=6 LANE=0"
api.platform.config.switch.0.portIndex.2.lane.1.portMapping text "LOG=2 EPL=6 LANE=1"
api.platform.config.switch.0.portIndex.2.lane.2.portMapping text "LOG=2 EPL=6 LANE=2"
api.platform.config.switch.0.portIndex.2.lane.3.portMapping text "LOG=2 EPL=6 LANE=3"
api.platform.config.switch.0.portIndex.3.portMapping text "LOG=3 PCIE=0"
api.platform.config.switch.0.portIndex.4.portMapping text "LOG=4 PCIE=2"
#=============================================================================#
# Interface type for the the given switch port
# Optional configuration. Default is NONE or specified by port.default.
# NONE, SFPP, QSFP_LANE0, QSFP_LANE1, QSFP_LANE2, QSFP_LANE3
#api.platform.config.switch.0.port.default.interfaceType text NONE
api.platform.config.switch.0.portIndex.1.interfaceType text QSFP_LANE0
api.platform.config.switch.0.portIndex.2.interfaceType text QSFP_LANE0
#=============================================================================#
# The maximum port speed at which the port will be operated. This is used
# to allocate scheduler bandwidth to the ports.
#
# Optional configuration. Default is automatically selected per port type
# EPL -> 2.5G
# PCIE_X1 -> 10G
# PCIE_X4 -> 50G
# PCIE_X8 -> 50G
# TE -> 100G
# LOOPBACK -> 25G
#
api.platform.config.switch.0.portIndex.0.speed int 10000
# QSFP0
api.platform.config.switch.0.portIndex.1.speed int 100000
api.platform.config.switch.0.portIndex.2.speed int 100000
#api.platform.config.switch.0.portIndex.3.speed int 1000
#api.platform.config.switch.0.portIndex.4.speed int 1000
#api.FM10000.schedMode text static
#=============================================================================#
# Ethernet mode for the the given switch port
# Optional configuration. Default is DISABLED or specified by port.default.
#
# EPL ports defaulted to 10G
api.platform.config.switch.0.port.default.ethernetMode text DISABLED
#
#
#
api.platform.config.switch.0.portIndex.1.ethernetMode text AUTODETECT
#api.platform.config.switch.0.portIndex.2.ethernetMode text 10GBase-SR
api.platform.config.switch.0.portIndex.2.ethernetMode text AUTODETECT
#api.platform.config.switch.0.portIndex.5.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.6.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.7.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.8.ethernetMode text DISABLED
#=============================================================================#
# Port capability for the the given switch port
# Optional configuration. Default is NONE or specified by port.default.
# NONE, LAG, ROUTE, 10M, 100M, 1G, 2PT5G, 10G, 25G, 40G, 100G, SW_LED
# Use comma delimited for multiple entries, no spaces.
# Backplane ports get default value
api.platform.config.switch.0.port.default.capability text NONE
# SFPP ports
api.platform.config.switch.0.portIndex.1.capability text LAG,ROUTE,10G,40G,100G,SW_LED
api.platform.config.switch.0.portIndex.2.capability text LAG,ROUTE,10G,40G,100G,SW_LED
#=============================================================================#
# Lane polarity for the the given switch port
# Optional configuration. Default is INVERT_NONE or specified by port.default.
# INVERT_NONE, INVERT_RX, INVERT_TX, INVERT_RX_TX
api.platform.config.switch.0.port.default.lanePolarity text INVERT_NONE
#=============================================================================#
# SERDES preCursor value for DA cables for the the given switch port
# Optional configuration. Default is 0 or specified by port.default.
api.platform.config.switch.0.port.default.preCursorCopper int 0
#=============================================================================#
# Unique 32-bit value associated with a port for the shared library
# If not specified then this value is default to port.default.hwResourceId
#
# Select a hwResourceId per port (zero base)
#
#api.platform.config.switch.0.port.default.hwResourceId int -1
#api.platform.config.switch.0.portIndex.1.hwResourceId int 0
#api.platform.config.switch.0.portIndex.2.hwResourceId int 1
#api.platform.config.switch.0.portIndex.3.hwResourceId int 2
api.platform.config.switch.0.portIndex.1.hwResourceId int 0x000
api.platform.config.switch.0.portIndex.2.hwResourceId int 0x101
###############################################################################
# Shared library configurations
###############################################################################
#=============================================================================#
# Shared library name to load switch management function interfaces
# Optional, all switch management features are disabled if not set.
api.platform.config.switch.0.sharedLibraryName text libLTStdPlatform.so
#=============================================================================#
# Disable loading function interfaces
# Optional, all function interfaces will be loaded if not set.
# NONE, fmPlatformLibInitSwitch, fmPlatformLibResetSwitch, fmPlatformLibI2cWriteRead,
# fmPlatformLibSelectBus, fmPlatformLibGetPortXcvrState, fmPlatformLibSetPortXcvrState,
# fmPlatformLibSetPortLed, fmPlatformLibEnablePortIntr, fmPlatformLibGetPortIntrPending
# Use comma delimited for multiple entries, no spaces.
api.platform.config.switch.0.sharedLibrary.disable text GetPortIntrPending,EnablePortIntr
#=============================================================================#
# Specifies what interface is used as I2C master to access
# the port logic devices.
api.platform.lib.config.bus0.i2cDevName text switchI2C
#=============================================================================#
# PCA mux configuration
#
api.platform.lib.config.pcaMux.count int 2
api.platform.lib.config.pcaMux.0.model text PCA9545
api.platform.lib.config.pcaMux.0.addr int 0x70
api.platform.lib.config.pcaMux.0.bus int 0
api.platform.lib.config.pcaMux.1.model text PCA9545
api.platform.lib.config.pcaMux.1.addr int 0x71
api.platform.lib.config.pcaMux.1.parent.index int 0
api.platform.lib.config.pcaMux.1.parent.value int 0x8
api.platform.lib.config.pcaMux.1.bus int 0
#=============================================================================#
# PCA I/O configuration
api.platform.lib.config.pcaIo.count int 2
api.platform.lib.config.pcaIo.0.model text PCA9505
api.platform.lib.config.pcaIo.0.addr int 0x20
api.platform.lib.config.pcaIo.0.parent.index int 0
api.platform.lib.config.pcaIo.0.parent.value int 0x4
api.platform.lib.config.pcaIo.0.bus int 0
api.platform.lib.config.pcaIo.1.model text PCA9635
api.platform.lib.config.pcaIo.1.addr int 0x6a
api.platform.lib.config.pcaIo.1.parent.index int 0
api.platform.lib.config.pcaIo.1.parent.value int 0x4
api.platform.lib.config.pcaIo.1.bus int 0
#=============================================================================#
# SFP+ pins offset from basePin
#api.platform.lib.config.xcvrState.default.modAbs.pin int 0
#api.platform.lib.config.xcvrState.default.rxLos.pin int 1
#api.platform.lib.config.xcvrState.default.txDisable.pin int 2
#api.platform.lib.config.xcvrState.default.txFault.pin int 3
#api.platform.lib.config.xcvrState.default.modPrsL.pin int 0
#api.platform.lib.config.xcvrState.default.intL.pin int 1
#api.platform.lib.config.xcvrState.default.resetL.pin int 2
#api.platform.lib.config.xcvrState.default.lpMode.pin int 3
api.platform.lib.config.xcvrState.default.modPrsL.pin int 2
api.platform.lib.config.xcvrState.default.intL.pin int 1
api.platform.lib.config.xcvrState.default.resetL.pin int 3
api.platform.lib.config.xcvrState.default.lpMode.pin int 0
#=============================================================================#
# Number of hwResourceId required (4 SFPP ports)
#
api.platform.lib.config.hwResourceId.count int 2
api.platform.config.switch.0.portIndex.1.hwResourceId int 0
api.platform.config.switch.0.portIndex.2.hwResourceId int 1
#=============================================================================#
# Hardware resource configuration
#
# zQSFP0
api.platform.lib.config.hwResourceId.0.interfaceType text QSFP
api.platform.lib.config.hwResourceId.0.xcvrI2C.busSelType text PCAMUX
api.platform.lib.config.hwResourceId.0.xcvrI2C.pcaMux.index int 1
api.platform.lib.config.hwResourceId.0.xcvrI2C.pcaMux.value int 0x4
api.platform.lib.config.hwResourceId.0.xcvrState.pcaIo.index int 0
api.platform.lib.config.hwResourceId.0.xcvrState.pcaIo.basePin int 0
api.platform.lib.config.hwResourceId.0.portLed.0.type text PCA
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.index int 1
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.pin int 0
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.usage text LINK,TRAFFIC,40G,100G
api.platform.lib.config.hwResourceId.1.interfaceType text QSFP
api.platform.lib.config.hwResourceId.1.xcvrI2C.busSelType text PCAMUX
api.platform.lib.config.hwResourceId.1.xcvrI2C.pcaMux.index int 1
api.platform.lib.config.hwResourceId.1.xcvrI2C.pcaMux.value int 0x8
api.platform.lib.config.hwResourceId.1.xcvrState.pcaIo.index int 0
api.platform.lib.config.hwResourceId.1.xcvrState.pcaIo.basePin int 8
api.platform.lib.config.hwResourceId.1.portLed.0.type text PCA
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.index int 1
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.pin int 1
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.usage text LINK,TRAFFIC,40G,100G

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driver/rdif Executable file
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#! /bin/sh
case "$1" in
start)
rdifd -v
;;
stop)
rdifd stop
;;
restart)
$0 stop && $0 start
;;
status)
;;
*)
echo "Usage: $0 {start|stop|restart}"
exit 1
;;
esac

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include/librdi.h Executable file
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#ifndef _LIBRDUSR_H_
#define _LIBRDUSR_H_
#pragma pack(push) /* push current alignment to stack */
#pragma pack(1) /* set alignment to 1 byte boundary */
enum rdi_conf {
RDI_INIT=1,
RDI_CLEAR,
RDI_CLEAR_GROUP,
RDI_SET_CFG,
RDI_SET_DROP,
RDI_SET_DIR,
RDI_SET_MIR,
RDI_GET_CFG,
RDI_INSTALL,
RDI_INSTALL_GROUP,
RDI_GET_CNT,
RDI_ENTRY_REMOVE,
RDI_ENTRY_QUERY,
RDI_ENTRY_QUERY_LIST,
RDI_GET_DEV_NUM,
RDI_SET_PORT_MASK,
RDI_GET_PORT_MASK,
RDI_SET_PERMIT,
RDI_SET_MOD0=49,
RDI_SET_MOD1=50,
RDI_SET_MOD2,
RDI_SET_L2_HASH,
RDI_SET_L3_HASH,
RDI_ADD_RULE,
RDI_LBG_QUERY_LIST,
RDI_LBG_PORT_QUERY_LIST,
RDI_LBG_REMOVE,
RDI_LBG_ADD,
RDI_LBG_PORT_REMOVE,
RDI_LBG_PORT_ADD,
RDI_GET_L2_HASH,
RDI_GET_L3_HASH,
RDI_GET_PORT_LINK,
RDI_GET_TEMP,
RDI_READ_PHY=100,
RDI_WRITE_PHY,
RDI_CPLD_READ,
RDI_CPLD_WRITE,
RDI_BP_READ,
RDI_BP_WRITE,
RDI_GET_GPIO_DIR,
RDI_SET_GPIO_DIR,
RDI_GET_GPIO,
RDI_SET_GPIO,
RDI_GET_REG,
RDI_SET_REG,
RDI_GET_VLAN_STAT=200,
RDI_GET_STAT,
RDI_GET_POWER,
} ;
enum rdi_action {
RDI_ACT_PERMIT=0,
RDI_ACT_DROP=1,
RDI_ACT_TRAP, //2
RDI_ACI_MIRROR, //3
RDI_ACT_LOG, //4
RDI_ACT_COUNT, //5
RDI_ACT_NOTIFY, //6
RDI_ACT_POLICE, //7
RDI_ACT_SET_VLAN, //8
RDI_ACT_SET_VLAN_PRI, //9
RDI_ACT_SET_SWITCH_PRI, //10
RDI_ACT_SET_DSCP, //11
RDI_ACT_SET_USER, //12
RDI_ACT_LOAD_BALANCE, //13
RDI_ACT_TRAP_ALWAYS, //14
RDI_ACT_REDIRECT, //15
RDI_ACT_NOROUTE, //16
RDI_ACT_ROUTE, //17
} ;
typedef struct rdi_udf_s {
short flag;
unsigned int offset;
unsigned int data;
unsigned int mask;
} rdi_udf_t;
typedef struct rdi_mac_s {
short flag;
unsigned char mac[6];
} rdi_mac_t;
typedef struct rdi_ip6_s {
short flag;
unsigned char ip[16];
} rdi_ip6_t;
typedef struct rdi_mem {
int group;
int rule_id;
int rule_act;
int port;
int redir_port;
int src_port;
int dst_port;
unsigned int src_ip;
unsigned int dst_ip;
unsigned int src_ip_mask;
unsigned int dst_ip_mask;
int src_port_mask;
int dst_port_mask;
int src_port_max;
int dst_port_max;
int ip_protocol;
int vlan;
int vlan_mask;
int vlan_max;
int mirror_port;
int mpls_type;
int mpls_label;
short mpls_exp_bits;
short mpls_s_bit;
int mpls_label_mask;
short mpls_exp_bits_mask;
short mpls_s_bit_mask;
int ether_type;
rdi_udf_t rdi_udf;
rdi_mac_t src_mac;
rdi_mac_t dst_mac;
rdi_ip6_t src_ip6;
rdi_ip6_t dst_ip6;
rdi_ip6_t src_ip6_mask;
rdi_ip6_t dst_ip6_mask;
int vlan_act;
int vlan_pri_act;
int vlan_tag;
int usr_act;
} rdi_mem_t;
typedef struct rdi_query_rule {
rdi_mem_t rdi_mem;
int ret;
} rdi_query_rule_t;
typedef struct rdi_id_list {
unsigned int rule_num;
unsigned char id_list[2048];
} rdi_id_list_t;
typedef struct rdi_query_list {
rdi_id_list_t rdi_id_list;
int ret;
}rdi_query_list_t;
typedef struct rdi_vlan_stat_cnt {
unsigned long long vland;
unsigned long long tvlan;
unsigned long long tvland;
}rdi_vlan_stat_cnt_t;
typedef struct rdib_stat_cnt {
unsigned long long total;
unsigned long long txnoerror;
unsigned long long rxnoerror;
unsigned long long rxdrop;
unsigned long long txdrop;
}rdib_stat_cnt_t;
typedef struct rdif_stat_cnt {
unsigned long long cntRxUcstPkts;
unsigned long long cntRxUcstPktsNonIP;
unsigned long long cntRxUcstPktsIPv4;
unsigned long long cntRxUcstPktsIPv6;
unsigned long long cntRxBcstPkts;
unsigned long long cntRxBcstPktsNonIP;
unsigned long long cntRxBcstPktsIPv4;
unsigned long long cntRxBcstPktsIPv6;
unsigned long long cntRxMcstPkts;
unsigned long long cntRxMcstPktsNonIP;
unsigned long long cntRxMcstPktsIPv4;
unsigned long long cntRxMcstPktsIPv6;
unsigned long long cntRxPausePkts;
unsigned long long cntRxCBPausePkts;
unsigned long long cntRxFCSErrors;
unsigned long long cntRxSymbolErrors;
unsigned long long cntRxFrameSizeErrors;
unsigned long long cntRxMinTo63Pkts;
unsigned long long cntRx64Pkts;
unsigned long long cntRx65to127Pkts;
unsigned long long cntRx128to255Pkts;
unsigned long long cntRx256to511Pkts;
unsigned long long cntRx512to1023Pkts;
unsigned long long cntRx1024to1522Pkts;
unsigned long long cntRx1523to2047Pkts;
unsigned long long cntRx2048to4095Pkts;
unsigned long long cntRx4096to8191Pkts;
unsigned long long cntRx8192to10239Pkts;
unsigned long long cntRx10240toMaxPkts;
unsigned long long cntRxFragmentPkts;
unsigned long long cntRxUndersizedPkts;
unsigned long long cntRxJabberPkts;
unsigned long long cntRxOversizedPkts;
unsigned long long cntRxGoodOctets;
unsigned long long cntRxOctetsNonIp;
unsigned long long cntRxOctetsIPv4;
unsigned long long cntRxOctetsIPv6;
unsigned long long cntRxBadOctets;
unsigned long long cntRxPriorityPkts;
unsigned long long cntRxPriorityOctets;
unsigned long long cntTxUcstPkts;
unsigned long long cntTxBcstPkts;
unsigned long long cntTxMcstPkts;
unsigned long long cntTxPausePkts;
unsigned long long cntTxFCSErroredPkts;
unsigned long long cntTxErrorDropPkts;
unsigned long long cntTxTimeOutPkts;
unsigned long long cntTxLoopbackPkts;
unsigned long long cntTxMinTo63Pkts;
unsigned long long cntTx64Pkts;
unsigned long long cntTx65to127Pkts;
unsigned long long cntTx128to255Pkts;
unsigned long long cntTx256to511Pkts;
unsigned long long cntTx512to1023Pkts;
unsigned long long cntTx1024to1522Pkts;
unsigned long long cntTx1523to2047Pkts;
unsigned long long cntTx2048to4095Pkts;
unsigned long long cntTx4096to8191Pkts;
unsigned long long cntTx8192to10239Pkts;
unsigned long long cntTx10240toMaxPkts;
unsigned long long cntTxOctets;
unsigned long long cntTxErrorOctets;
unsigned long long cntTxCMDropPkts;
unsigned long long cntFIDForwardedPkts;
unsigned long long cntFloodForwardedPkts;
unsigned long long cntSpeciallyHandledPkts;
unsigned long long cntParseErrDropPkts;
unsigned long long cntParityErrorPkts;
unsigned long long cntTrappedPkts;
unsigned long long cntPauseDropPkts;
unsigned long long cntSTPDropPkts;
unsigned long long cntReservedTrapPkts;
unsigned long long cntSecurityViolationPkts;
unsigned long long cntVLANTagDropPkts;
unsigned long long cntVLANIngressBVPkts;
unsigned long long cntVLANEgressBVPkts;
unsigned long long cntGlortMissDropPkts;
unsigned long long cntFFUDropPkts;
unsigned long long cntPolicerDropPkts;
unsigned long long cntTTLDropPkts;
unsigned long long cntCmPrivDropPkts;
unsigned long long cntSmp0DropPkts;
unsigned long long cntSmp1DropPkts;
unsigned long long cntRxHog0DropPkts;
unsigned long long cntRxHog1DropPkts;
unsigned long long cntTxHog0DropPkts;
unsigned long long cntTxHog1DropPkts;
unsigned long long cntRateLimit0DropPkts;
unsigned long long cntRateLimit1DropPkts;
unsigned long long cntBadSmpDropPkts;
unsigned long long cntTriggerDropRedirPkts;
unsigned long long cntTriggerDropPkts;
unsigned long long cntTriggerRedirPkts;
unsigned long long cntTriggerMirroredPkts;
unsigned long long cntBroadcastDropPkts;
unsigned long long cntDLFDropPkts;
unsigned long long cntRxCMDropPkts;
unsigned long long cntUnderrunPkts;
unsigned long long cntOverrunPkts;
unsigned long long cntCorruptedPkts;
unsigned long long cntStatsDropCountTx;
unsigned long long cntStatsDropCountRx;
} rdif_stat_cnt_t;
typedef struct _rdi_hashRotationValue {
/** The shift amount in the operation is one plus this value. */
unsigned char exponent;
/** The amount the input hash value is multiplied by before shifting. */
unsigned short mantissa;
} rdi_hashRotationValue;
#define RDI_L2_HASH_SMAC 1<<0
#define RDI_L2_HASH_DMAC 1<<1
#define RDI_L2_HASH_ETHER_TYPE 1<<2
#define RDI_L2_HASH_VLAN_ID 1<<3
#define RDI_L2_HASH_VLAN_PRI 1<<4
#define RDI_L2_HASH_SYM_MAC 1<<5
#define RDI_L2_HASH_VLAN2_ID 1<<6
#define RDI_L2_HASH_VLAN2_PRI 1<<7
#define RDI_L2_HASH_PROFILE_IDX 1<<24
typedef struct rdi_l2_hash {
unsigned int l2_hash_set;
/** Indicates the inclusion bit mask for the SMAC field.
* The valid range is 0 (disable) to 0xffffffffffff (all bits
* included). The default is 0xffffffffffff.
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
* */
unsigned int profile_index;
unsigned char src_mac_mask[6];
/** Indicates the inclusion bit mask for the DMAC field.
* The valid range is 0 (disable) to 0xffffffffffff (all bits
* included). The default is 0xffffffffffff.
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*/
unsigned char dst_mac_mask[6];
/** Indicates the inclusion bit mask for the EtherType field.
* The valid range is 0 (disable) to 0xffff (all bits
* included). The default is 0xffff.
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
* */
unsigned int ether_type_mask;
/** Indicates the inclusion bit mask for the VLAN ID 1 field.
* The valid range is 0 (disable) to 0xfff (all bits
* included). The default is 0xfff.
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*/
unsigned int vlan_id_mask;
/** Indicates the inclusion bit mask for the VLAN Priority 1 field.
* The valid range is 0 (disable) to 0xf. The default is 0xf (all
* bits included).
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*/
unsigned int vlan_pri;
/** Indicates the inclusion bit mask for the VLAN ID 1 field.
* The valid range is 0 (disable) to 0xfff (all bits
* included). The default is 0xfff.
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*/
unsigned int vlan2_id_mask;
/** Indicates the inclusion bit mask for the VLAN Priority 1 field.
* The valid range is 0 (disable) to 0xf. The default is 0xf (all
* bits included).
*
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*/
unsigned int vlan2_pri;
/** Enable symmetrizing of the source and destination MAC fields.
* The default is FALSE.
*
* */
unsigned int sym_mac;
} rdi_l2_hash_t;
#define RDI_L3_HASH_SIP 1<<0
#define RDI_L3_HASH_DIP 1<<1
#define RDI_L3_HASH_SPORT 1<<2
#define RDI_L3_HASH_DPORT 1<<3
#define RDI_L3_HASH_DSCP 1<<4
#define RDI_L3_HASH_ISL_USR 1<<5
#define RDI_L3_HASH_PROTO 1<<6
#define RDI_L3_HASH_FLOW 1<<7
#define RDI_L3_HASH_SYM_L3_FIELDS 1<<8
#define RDI_L3_HASH_SYM_L4_FIELDS 1<<9
#define RDI_L3_HASH_CUSTOM 1<<10
#define RDI_L3_HASH_RND_NEXT_HOP 1<<11
#define RDI_L3_HASH_RND_OTHER 1<<12
#define RDI_L3_HASH_RND_ONLY 1<<13
typedef struct rdi_l3_hash {
unsigned int l3_hash_set;
unsigned int profile_index;
/** Indicates the inclusion byte mask for the SIP field. Each bit of this
* mask indicates a full byte of the SIP with bit 0 corresponding to
* byte 0, bit 1 to byte 1, etc. The valid range is 0 (disable) to
* 0xffff (all bytes included). The default is 0xffff.
* \lb\lb
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*
* */
unsigned int src_ip_mask;
/** Indicates the inclusion byte mask for the DIP field. Each bit of this
* mask indicates a full byte of the SIP with bit 0 corresponding to
* byte 0, bit 1 to byte 1, etc. The valid range is 0 (disable) to
* 0xffff (all bytes included). The default is 0xffff.
* \lb\lb
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*
* */
unsigned int dst_ip_mask;
/** Indicates the inclusion bit mask for the layer 4 source port.
* The valid range is 0 (disable) to 0xffff (all bits included).
* The default is 0xffff.
* \lb\lb
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*
* */
unsigned int src_port_mask;
/** Indicates the inclusion bit mask for the layer 4 destination port.
* The valid range is 0 (disable) to 0xffff (all bits included).
* The default is 0xffff.
* \lb\lb
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*
* */
unsigned int dst_port_mask;
/** Indicates the inclusion bit mask for the DSCP field value.
* The valid range is 0 (disable) to 0xff (all bits included).
* The default is 0xff.
*
* */
unsigned int dscp_mask;
/** Indicates the inclusion bit mask for the ISL_USER field value.
* The valid range is 0 (disable) to 0xff (all bits included).
* The default is 0.
*
* */
unsigned int isl_usr_mask;
/** Indicates the inclusion bit mask for the layer 3 protocol field
* value. The valid range is 0 (disable) to 0xff (all bits included).
* The default is 0xff.
* \lb\lb
* Acts as a boolean
* and any value different then 0 will enable this specific key.
*
* */
unsigned int proto_mask;
/** Indicates the inclusion byte mask for the custom parser field value.
* This value is dependent on the parser microcode and FFU rules. Each
* bit of this mask indicates a full byte of the custome parser field
* with bit 0 corresponding to byte 0, bit 1 to byte 1, etc. The valid
* range is 0 (disable) to 0xff (all bytes included). The default is 0.
*
* \chips FM6000 */
unsigned int custom_mask;
/** Indicates the inclusion bit mask for the IPv6 flow field value.
* The valid range is 0 (disabled) to 0xfffff (all bits included).
* The default is 0xfffff.
*
* */
unsigned int flow_mask;
/** Enable symmetrizing of the SIP & DIP fields. This ensures that frames
* with opposite SIP & DIP fields will hash the same with respect to
* those fields. The default is FALSE.
*
* */
unsigned char sym_l3_fields;
/** Enable symmetrizing of the layer 4 source and destination port fields.
* This ensures that frames with opposite source & destination port fields
* will hash the same with respect to those fields. The default is FALSE.
*
* */
unsigned char sym_l4_fields;
/** Enable use of the hardware PTable to facilitate improved hash results.
* Note that this will require configuring the PTable (register
* HASH_LAYER3_PTABLE). The default
* is FALSE.
*
* \chips FM6000 */
unsigned char use_ptable;
/** Enable producing a random value to the next-hop evaluation stage.
* Default is FALSE.
*
* \chips FM6000 */
unsigned char random_next_hop;
/** Enable producing a random value to other stages downstream of the
* hash calculation. Default is FALSE.
*
* \chips FM6000 */
unsigned char random_other;
/** If set to true, disable all hash computation except for the random
* outputs, if they are enabled. Default is FALSE.
*
* \chips FM6000 */
unsigned char random_only;
} rdi_l3_hash_t;
typedef union rdi_stat_cnt {
rdib_stat_cnt_t rdib;
rdif_stat_cnt_t rdif;
}rdi_stat_cnt_t;
typedef struct rdi_rule_stat_cnt {
unsigned long long counter;
}rdi_rule_stat_cnt_t;
typedef struct rdi_rule_stat {
rdi_rule_stat_cnt_t rdi_rule_stat_cnt;
int ret_val;
}rdi_rule_stat_t;
typedef struct rdi_stat {
rdi_stat_cnt_t rdi_stat_cnt;
int ret_val;
}rdi_stat_t;
typedef struct rdi_vlan_stat {
rdi_vlan_stat_cnt_t rdi_vlan_stat_cnt;
int ret_val;
}rdi_vlan_stat_t;
typedef struct rdi_sfi_diag {
unsigned short tx_power;
unsigned short rx_power;
unsigned int rsv[3];
} rdi_sfi_diag_t;
typedef enum rdi_type_s {
RDI_BCM_DEV=1,
RDI_FLCM_DEV
}rdi_type_t;
typedef struct if_rdi {
int rdi_cmd;
int unit;
int cfg;
rdi_mem_t rdi_mem;
int if_index; /* network device index of management interface */
int rule_id;
int group;
int port;
unsigned int mask;
rdi_query_list_t rdi_query_list;
rdi_rule_stat_t rdi_rule_stat;
rdi_vlan_stat_t rdi_vlan_stat;
rdi_stat_t rdi_stat;
rdi_l2_hash_t l2_hash;
rdi_l3_hash_t l3_hash;
int action;
/* diagnostic fieds */
int phy_addr;
int addr;
int dev;
int val;
} if_rdi_t;
typedef struct rdi_lbg_list {
int num;
int list[16];
} rdi_lbg_list_t;
typedef struct rdi_lbg_query_list {
rdi_lbg_list_t rdi_lbg_list;
int ret;
}rdi_lbg_query_list_t;
typedef struct if_rdi_lbg {
int rdi_cmd;
int unit;
rdi_lbg_query_list_t rdi_query_list;
int lbg;
int port;
} if_rdi_lbg_t;
typedef struct rdi_bp_data_list {
unsigned int num;
unsigned char list[2048];
} rdi_bp_data_t;
typedef struct rdi_bp_query_data {
rdi_bp_data_t data;
int ret;
}rdi_bp_query_data_t;
typedef struct if_rdi_bp {
int rdi_cmd;
int unit;
rdi_bp_query_data_t bp_query_data;
int dev;
int addr;
} if_rdi_bp_t;
typedef struct rdi_mask {
unsigned char ingress[16];
unsigned char egress[16];
int ret_val;
} rdi_mask_t;
typedef struct if_rdi_mask {
unsigned int rdi_cmd;
unsigned int unit;
rdi_mask_t mask;
} if_rdi_mask_t;
int rdi_get_dev_num(rdi_type_t rdi_type);
int rdi_init(int unit, int if_index, rdi_type_t rdi_type);
int rdi_set_mod0(int unit, rdi_type_t rdi_type);
int rdi_set_mod1(int unit, rdi_type_t rdi_type);
int rdi_set_mod2(int unit, rdi_type_t rdi_type);
int rdi_set_cfg(int unit, int cfg, rdi_type_t rdi_type);
int rdi_entry_remove(int unit, int rule_id, int group, rdi_type_t rdi_type);
int rdi_get_cfg(int unit, rdi_type_t rdi_type);
int rdi_get_temp(int unit, rdi_type_t rdi_type);
int rdi_add_rule_drop(int unit, rdi_mem_t *rdi_mem, rdi_type_t rdi_type);
int rdi_add_rule_permit(int unit, rdi_mem_t *rdi_mem, rdi_type_t rdi_type);
int rdi_add_rule(int unit, rdi_mem_t *rdi_mem, int action, rdi_type_t rdi_type);
int rdi_add_rule_dir(int unit, rdi_mem_t *rdi_mem, rdi_type_t rdi_type);
int rdi_add_rule_mir(int unit, rdi_mem_t *rdi_mem, rdi_type_t rdi_type);
int rdi_install_rules(int unit, rdi_type_t rdi_type);
int rdi_clear_rules(int unit, rdi_type_t rdi_type);
int rdi_install_rules_group(int unit, int group, rdi_type_t rdi_type);
int rdi_clear_rules_group(int unit, int group, rdi_type_t rdi_type);
int rdi_entry_query(int unit, rdi_mem_t *rdi_mem, rdi_type_t rdi_type);
int rdi_get_rule_counters(int unit, int rule_id, int group, void *val, rdi_type_t rdi_type);
int rdi_entry_query_list(int unit, int group, rdi_query_list_t *rdi_query_list, rdi_type_t rdi_type);
int rdi_get_vlan_stat(int unit, int port, rdi_vlan_stat_cnt_t *rdi_vlan_stat_cnt, rdi_type_t rdi_type);
int rdi_get_stat(int unit, int port, rdi_stat_cnt_t *val, rdi_type_t rdi_type);
int rdi_get_rule_stat(int unit, int rule_id, int group, rdi_rule_stat_cnt_t *rdi_rule_stat_cnt, rdi_type_t rdi_type);
int rdi_read_phy(int unit, int phy_addr, int dev, int addr, rdi_type_t rdi_type);
int rdi_write_phy(int unit, int phy_addr, int dev, int addr, int val, rdi_type_t rdi_type);
int rdi_get_gpio_dir(int unit, int gpio, rdi_type_t rdi_type);
int rdi_set_gpio_dir(int unit, int gpio, int dir, int val, rdi_type_t rdi_type);
int rdi_get_gpio(int unit, int gpio, rdi_type_t rdi_type);
int rdi_set_gpio(int unit, int gpio, int val, rdi_type_t rdi_type);
int rdi_get_reg(int unit, unsigned int addr, unsigned int *val, rdi_type_t rdi_type);
int rdi_set_reg(int unit, unsigned int addr, unsigned int val, rdi_type_t rdi_type);
int rdi_get_power(int unit, int port, rdi_sfi_diag_t *sfi_diag, rdi_type_t rdi_type);
int rdi_set_port_mask(int unit, int port, unsigned int mask, rdi_type_t rdi_type);
int rdi_get_port_mask(int unit, int port, unsigned char *mask, rdi_type_t rdi_type);
int rdi_set_mask(int unit, rdi_mask_t *mask, rdi_type_t rdi_type);
int rdi_get_mask(int unit, rdi_mask_t *mask, rdi_type_t rdi_type);
int rdi_cpld_write(int unit, int addr, unsigned int val, rdi_type_t rdi_type);
int rdi_cpld_read(int unit, int addr, unsigned char *val, rdi_type_t rdi_type);
int rdi_set_l2_hash(int unit, rdi_l2_hash_t *l2_hash, rdi_type_t rdi_type);
int rdi_set_l3_hash(int unit, rdi_l3_hash_t *l3_hash, rdi_type_t rdi_type);
int rdi_get_l2_hash(int unit, rdi_l2_hash_t *l2_hash, rdi_type_t rdi_type);
int rdi_get_l3_hash(int unit, rdi_l3_hash_t *l3_hash, rdi_type_t rdi_type);
int rdi_lbg_query_entry_list(int unit, struct rdi_lbg_query_list *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_lbg_port_query_entry_list(int unit, int lbg, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_lbg_remove(int unit, int lbg, rdi_type_t rdi_type);
int rdi_lbg_add(int unit, int *lbg, rdi_type_t rdi_type);
int rdi_lbg_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_lbg_port_add(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_get_port_link(int unit, int port, rdi_type_t rdi_type);
int rdi_bp_read(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_bp_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
#endif /* _RDD_LIB_H_ */

12
install Executable file
View File

@ -0,0 +1,12 @@
#! /bin/sh
BUILD=`pwd`
cd $BUILD/driver
make install
cd $BUILD/lib
make
# make local=1 install
make local=$1 install
cd $BUILD/util
# make local=1
make local=$1
make install

1340
lib/librdi.c Executable file
View File

@ -0,0 +1,1340 @@
/******************************************************************************/
/* */
/* bypass library, Copyright (c) 2004 Silicom, Ltd */
/* Corporation. */
/* */
/* This program is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU General Public License as published by */
/* the Free Software Foundation, located in the file LICENSE. */
/* */
/* Ver 1.0.0 */
/* */
/* librdi.c */
/* */
/******************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <errno.h>
#include <string.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <sys/un.h>
#include <unistd.h>
#include "../include/librdi.h"
#define RDI_SOCK_PATH "/var/run/rdictl.sock"
#define RDIF_SOCK_PATH "/var/run/rdifctl.sock"
#if 0
static void dumpBytes(unsigned char *bytes, unsigned int len)
{
unsigned int cnt;
for (cnt = 0 ; cnt < len ; cnt++) {
printf("%02x", bytes[cnt]);
if (cnt % 4 == 3) {
printf(" ");
}
if (cnt % 32 == 31) {
printf("\n");
}
}
printf("\n");
}
#endif
static int send_cmd(if_rdi_t *if_rdi, void * ret, int n, rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {
perror("librdi socket");
return -1;
}
remote.sun_family = AF_UNIX;
if (rdi_type==RDI_FLCM_DEV)
strcpy(remote.sun_path, RDIF_SOCK_PATH);
else
strcpy(remote.sun_path, RDI_SOCK_PATH);
len = strlen(remote.sun_path) + sizeof(remote.sun_family);
if (connect(s, (struct sockaddr *)&remote, len) == -1) {
perror("librdi connect");
close(s);
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
return -1;
}
if ((t=recv(s, ret, n, 0)) < 0) {
perror("librdi recv");
close(s);
return -1;
}
close(s);
return 0;
}
int rdi_get_dev_num(rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_DEV_NUM;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
static int send_cmd_query_rule(if_rdi_t *if_rdi, struct rdi_query_rule *rdi_query_rule,rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {
perror("librdi socket");
return -1;
}
remote.sun_family = AF_UNIX;
if (rdi_type==RDI_FLCM_DEV)
strcpy(remote.sun_path, RDIF_SOCK_PATH);
else
strcpy(remote.sun_path, RDI_SOCK_PATH);
len = strlen(remote.sun_path) + sizeof(remote.sun_family);
if (connect(s, (struct sockaddr *)&remote, len) == -1) {
perror("librdi connect");
close(s);
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
return -1;
}
if ((t=recv(s, rdi_query_rule, sizeof(rdi_query_rule_t), 0)) < 0) {
perror("librdi recv");
close(s);
return -1;
}
close(s);
return 0;
}
static int send_cmd_query_list(if_rdi_t *if_rdi, struct rdi_query_list *rdi_query_list,rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {
perror("librdi socket");
return -1;
}
remote.sun_family = AF_UNIX;
if (rdi_type==RDI_FLCM_DEV)
strcpy(remote.sun_path, RDIF_SOCK_PATH);
else
strcpy(remote.sun_path, RDI_SOCK_PATH);
len = strlen(remote.sun_path) + sizeof(remote.sun_family);
if (connect(s, (struct sockaddr *)&remote, len) == -1) {
perror("librdi connect");
close(s);
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
return -1;
}
if ((t=recv(s, rdi_query_list, sizeof(rdi_query_list_t), 0)) < 0) {
perror("librdi recv");
close(s);
return -1;
}
close(s);
return 0;
}
static int send_cmd_lbg_query_list(if_rdi_t *if_rdi, struct rdi_lbg_query_list *rdi_lbg_query_list,rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {
perror("librdi socket");
return -1;
}
remote.sun_family = AF_UNIX;
if (rdi_type==RDI_FLCM_DEV)
strcpy(remote.sun_path, RDIF_SOCK_PATH);
else
strcpy(remote.sun_path, RDI_SOCK_PATH);
len = strlen(remote.sun_path) + sizeof(remote.sun_family);
if (connect(s, (struct sockaddr *)&remote, len) == -1) {
perror("librdi connect");
close(s);
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
return -1;
}
if ((t=recv(s, rdi_lbg_query_list, sizeof(rdi_lbg_query_list_t), 0)) < 0) {
perror("librdi recv");
close(s);
return -1;
}
close(s);
return 0;
}
int rdi_init(int unit, int if_index, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_INIT;
if_rdi.unit=unit;
if (rdi_type==RDI_FLCM_DEV)
if_rdi.if_index=if_index;
if (!send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type))
return ret;
return -1;
}
int rdi_get_cfg(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_CFG;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_get_temp(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_TEMP;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_get_port_link(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_PORT_LINK;
if_rdi.unit=unit;
if_rdi.port=port;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_install_rules(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_INSTALL;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_install_rules_group(int unit, int group, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_INSTALL_GROUP;
if_rdi.unit=unit;
if_rdi.group=group;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_clear_rules(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_CLEAR;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_clear_rules_group(int unit, int group, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_CLEAR_GROUP;
if_rdi.unit=unit;
if_rdi.group=group;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_set_cfg(int unit, int cfg, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_SET_CFG;
if_rdi.cfg=cfg;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_set_mod0(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_SET_MOD0;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_set_mod1(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_SET_MOD1;
if_rdi.unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_set_mod2(int unit, rdi_type_t rdi_type){