Upstream release 6.0.10.7.30.1

This commit is contained in:
Silicom Ltd 2019-06-23 13:21:48 +00:00 committed by WeebDataHoarder
parent cb2e20770c
commit ecabff31a7
12 changed files with 2960 additions and 596 deletions

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@ -19,7 +19,6 @@ install:
mkdir -p $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
install rdif $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)
mkdir -p /etc/rdi
install -m 444 fm_platform_attributes.cfg /etc/rdi
ifeq (,$(en64))
install ./32/rdifd $(INSTALL_MOD_PATH)$(PRDPATH_UTIL)

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@ -1,380 +0,0 @@
###########################################################
# Global configurations
###########################################################
#=========================================================#
#Debug configuration flag
#Optional Configuration. Default is NONE.
# CONFIG, MOD_STATE, MOD_INTR, MOD_TYPE, PLAT_LOG
# Use comma delimited for multiple entries, no spaces.
# api.platform.config.debug text CONFIG
#=========================================================#
# Total number of switches in the system
# Required configuration.
api.platform.config.numSwitches int 1
api.platform.config.switch.0.uioDevName text /dev/uio0
#=========================================================#
# Platform name
# Optional Configuration. Default is libertyTrail.
api.platform.config.platformName text rubyRapid
#=========================================================#
# Interrupt parameters
api.platform.config.switch.0.msiEnabled bool true
#####################################################################
# Switch configurations
#####################################################################
#===================================================================#
# Switch number for the specified switch index
# Note switch index is also the same as API sw argument.
# Switch number is the value that will be passed down to the shared
# library interfaces as well as kernel module driver interfaces.
# Optional configuration.
# If not specified then switch number is the same as switch index.
api.platform.config.switch.0.switchNumber int 0
#===================================================================#
# LED polling period, for software driven LED
# See SW_LED in port capabilities.
#optional configuration. Default 500 msec.
api.platform.config.switch.0.ledPollPeriodMsec int 200
api.platform.config.switch.0.ledBlinkMode text HW_ASSISTED
api.platform.config.switch.0.portIntrGpio int 6
api.platform.config.switch.0.i2cResetGpio int 5
#===================================================================#
#Transceiver management polling period
#optional configuration. Default 1000 msec.
#api.platform.config.switch.0.xcvrPollPeriodMsec int 0
#===================================================================#
# Total number of ports on the switch, including CPU port
# Required configuration
# This is the number of portIndex below
api.platform.config.switch.0.numPorts int 5
###############################################################################
# Port configurations
###############################################################################
# For receiving/transmitting packets to/from API using raw socket
# Changing pep number also requires swapping associated PCIE portMapping entries
#api.platform.config.switch.0.netDevName text p1p3
api.platform.config.switch.0.cpuPort int 4
api.platform.config.switch.0.bootCfg.mgmtPep int 2
# CPU port (PEP #8 --> PCIE x1)
api.platform.config.switch.0.portIndex.0.portMapping text "LOG=0 PCIE=8"
# SFPP
# QSFP0
api.platform.config.switch.0.portIndex.1.lane.0.portMapping text "LOG=1 EPL=0 LANE=0"
api.platform.config.switch.0.portIndex.1.lane.1.portMapping text "LOG=1 EPL=0 LANE=1"
api.platform.config.switch.0.portIndex.1.lane.2.portMapping text "LOG=1 EPL=0 LANE=2"
api.platform.config.switch.0.portIndex.1.lane.3.portMapping text "LOG=1 EPL=0 LANE=3"
# QSFP1 (with different lane ordering)
api.platform.config.switch.0.portIndex.2.lane.0.portMapping text "LOG=2 EPL=6 LANE=0"
api.platform.config.switch.0.portIndex.2.lane.1.portMapping text "LOG=2 EPL=6 LANE=1"
api.platform.config.switch.0.portIndex.2.lane.2.portMapping text "LOG=2 EPL=6 LANE=2"
api.platform.config.switch.0.portIndex.2.lane.3.portMapping text "LOG=2 EPL=6 LANE=3"
api.platform.config.switch.0.portIndex.3.portMapping text "LOG=3 PCIE=0"
api.platform.config.switch.0.portIndex.4.portMapping text "LOG=4 PCIE=2"
#=============================================================================#
# Interface type for the the given switch port
# Optional configuration. Default is NONE or specified by port.default.
# NONE, SFPP, QSFP_LANE0, QSFP_LANE1, QSFP_LANE2, QSFP_LANE3
#api.platform.config.switch.0.port.default.interfaceType text NONE
api.platform.config.switch.0.portIndex.1.interfaceType text QSFP_LANE0
api.platform.config.switch.0.portIndex.2.interfaceType text QSFP_LANE0
#=============================================================================#
# The maximum port speed at which the port will be operated. This is used
# to allocate scheduler bandwidth to the ports.
#
# Optional configuration. Default is automatically selected per port type
# EPL -> 2.5G
# PCIE_X1 -> 10G
# PCIE_X4 -> 50G
# PCIE_X8 -> 50G
# TE -> 100G
# LOOPBACK -> 25G
#
api.platform.config.switch.0.portIndex.0.speed int 10000
# QSFP0
api.platform.config.switch.0.portIndex.1.speed int 100000
api.platform.config.switch.0.portIndex.2.speed int 100000
#api.platform.config.switch.0.portIndex.3.speed int 1000
#api.platform.config.switch.0.portIndex.4.speed int 1000
#api.FM10000.schedMode text static
#=============================================================================#
# Ethernet mode for the the given switch port
# Optional configuration. Default is DISABLED or specified by port.default.
#
# EPL ports defaulted to 10G
api.platform.config.switch.0.port.default.ethernetMode text DISABLED
#
#
#
api.platform.config.switch.0.portIndex.1.ethernetMode text AUTODETECT
#api.platform.config.switch.0.portIndex.2.ethernetMode text 10GBase-SR
api.platform.config.switch.0.portIndex.2.ethernetMode text AUTODETECT
#api.platform.config.switch.0.portIndex.5.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.6.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.7.ethernetMode text DISABLED
#api.platform.config.switch.0.portIndex.8.ethernetMode text DISABLED
#=============================================================================#
# Port capability for the the given switch port
# Optional configuration. Default is NONE or specified by port.default.
# NONE, LAG, ROUTE, 10M, 100M, 1G, 2PT5G, 10G, 25G, 40G, 100G, SW_LED
# Use comma delimited for multiple entries, no spaces.
# Backplane ports get default value
api.platform.config.switch.0.port.default.capability text NONE
# SFPP ports
api.platform.config.switch.0.portIndex.1.capability text LAG,ROUTE,10G,40G,100G,SW_LED
api.platform.config.switch.0.portIndex.2.capability text LAG,ROUTE,10G,40G,100G,SW_LED
#=============================================================================#
# Lane polarity for the the given switch port
# Optional configuration. Default is INVERT_NONE or specified by port.default.
# INVERT_NONE, INVERT_RX, INVERT_TX, INVERT_RX_TX
api.platform.config.switch.0.port.default.lanePolarity text INVERT_NONE
#=============================================================================#
# SERDES preCursor value for DA cables for the the given switch port
# Optional configuration. Default is 0 or specified by port.default.
api.platform.config.switch.0.port.default.preCursorCopper int 0
#=============================================================================#
# Unique 32-bit value associated with a port for the shared library
# If not specified then this value is default to port.default.hwResourceId
#
# Select a hwResourceId per port (zero base)
#
#api.platform.config.switch.0.port.default.hwResourceId int -1
#api.platform.config.switch.0.portIndex.1.hwResourceId int 0
#api.platform.config.switch.0.portIndex.2.hwResourceId int 1
#api.platform.config.switch.0.portIndex.3.hwResourceId int 2
api.platform.config.switch.0.portIndex.1.hwResourceId int 0x000
api.platform.config.switch.0.portIndex.2.hwResourceId int 0x101
###############################################################################
# Shared library configurations
###############################################################################
#=============================================================================#
# Shared library name to load switch management function interfaces
# Optional, all switch management features are disabled if not set.
api.platform.config.switch.0.sharedLibraryName text libLTStdPlatform.so
#=============================================================================#
# Disable loading function interfaces
# Optional, all function interfaces will be loaded if not set.
# NONE, fmPlatformLibInitSwitch, fmPlatformLibResetSwitch, fmPlatformLibI2cWriteRead,
# fmPlatformLibSelectBus, fmPlatformLibGetPortXcvrState, fmPlatformLibSetPortXcvrState,
# fmPlatformLibSetPortLed, fmPlatformLibEnablePortIntr, fmPlatformLibGetPortIntrPending
# Use comma delimited for multiple entries, no spaces.
api.platform.config.switch.0.sharedLibrary.disable text GetPortIntrPending,EnablePortIntr
#=============================================================================#
# Specifies what interface is used as I2C master to access
# the port logic devices.
api.platform.lib.config.bus0.i2cDevName text switchI2C
#=============================================================================#
# PCA mux configuration
#
api.platform.lib.config.pcaMux.count int 2
api.platform.lib.config.pcaMux.0.model text PCA9545
api.platform.lib.config.pcaMux.0.addr int 0x70
api.platform.lib.config.pcaMux.0.bus int 0
api.platform.lib.config.pcaMux.1.model text PCA9545
api.platform.lib.config.pcaMux.1.addr int 0x71
api.platform.lib.config.pcaMux.1.parent.index int 0
api.platform.lib.config.pcaMux.1.parent.value int 0x8
api.platform.lib.config.pcaMux.1.bus int 0
#=============================================================================#
# PCA I/O configuration
api.platform.lib.config.pcaIo.count int 2
api.platform.lib.config.pcaIo.0.model text PCA9505
api.platform.lib.config.pcaIo.0.addr int 0x20
api.platform.lib.config.pcaIo.0.parent.index int 0
api.platform.lib.config.pcaIo.0.parent.value int 0x4
api.platform.lib.config.pcaIo.0.bus int 0
api.platform.lib.config.pcaIo.1.model text PCA9635
api.platform.lib.config.pcaIo.1.addr int 0x6a
api.platform.lib.config.pcaIo.1.parent.index int 0
api.platform.lib.config.pcaIo.1.parent.value int 0x4
api.platform.lib.config.pcaIo.1.bus int 0
#=============================================================================#
# SFP+ pins offset from basePin
#api.platform.lib.config.xcvrState.default.modAbs.pin int 0
#api.platform.lib.config.xcvrState.default.rxLos.pin int 1
#api.platform.lib.config.xcvrState.default.txDisable.pin int 2
#api.platform.lib.config.xcvrState.default.txFault.pin int 3
#api.platform.lib.config.xcvrState.default.modPrsL.pin int 0
#api.platform.lib.config.xcvrState.default.intL.pin int 1
#api.platform.lib.config.xcvrState.default.resetL.pin int 2
#api.platform.lib.config.xcvrState.default.lpMode.pin int 3
api.platform.lib.config.xcvrState.default.modPrsL.pin int 2
api.platform.lib.config.xcvrState.default.intL.pin int 1
api.platform.lib.config.xcvrState.default.resetL.pin int 3
api.platform.lib.config.xcvrState.default.lpMode.pin int 0
#=============================================================================#
# Number of hwResourceId required (4 SFPP ports)
#
api.platform.lib.config.hwResourceId.count int 2
api.platform.config.switch.0.portIndex.1.hwResourceId int 0
api.platform.config.switch.0.portIndex.2.hwResourceId int 1
#=============================================================================#
# Hardware resource configuration
#
# zQSFP0
api.platform.lib.config.hwResourceId.0.interfaceType text QSFP
api.platform.lib.config.hwResourceId.0.xcvrI2C.busSelType text PCAMUX
api.platform.lib.config.hwResourceId.0.xcvrI2C.pcaMux.index int 1
api.platform.lib.config.hwResourceId.0.xcvrI2C.pcaMux.value int 0x4
api.platform.lib.config.hwResourceId.0.xcvrState.pcaIo.index int 0
api.platform.lib.config.hwResourceId.0.xcvrState.pcaIo.basePin int 0
api.platform.lib.config.hwResourceId.0.portLed.0.type text PCA
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.index int 1
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.pin int 0
api.platform.lib.config.hwResourceId.0.portLed.0.pcaIo.usage text LINK,TRAFFIC,40G,100G
api.platform.lib.config.hwResourceId.1.interfaceType text QSFP
api.platform.lib.config.hwResourceId.1.xcvrI2C.busSelType text PCAMUX
api.platform.lib.config.hwResourceId.1.xcvrI2C.pcaMux.index int 1
api.platform.lib.config.hwResourceId.1.xcvrI2C.pcaMux.value int 0x8
api.platform.lib.config.hwResourceId.1.xcvrState.pcaIo.index int 0
api.platform.lib.config.hwResourceId.1.xcvrState.pcaIo.basePin int 8
api.platform.lib.config.hwResourceId.1.portLed.0.type text PCA
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.index int 1
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.pin int 1
api.platform.lib.config.hwResourceId.1.portLed.0.pcaIo.usage text LINK,TRAFFIC,40G,100G

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@ -2,10 +2,11 @@
case "$1" in
start)
rdifd -v
#rdifd
;;
stop)
rdifd stop
rdifd stop
;;
restart)
$0 stop && $0 start

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@ -45,6 +45,34 @@ enum rdi_conf {
RDI_GET_PORT_LINK,
RDI_GET_TEMP,
RDI_MIR_QUERY_LIST,
RDI_MIR_PORT_QUERY_LIST,
RDI_MIR_REMOVE,
RDI_MIR_ADD,
RDI_MIR_PORT_REMOVE,
RDI_MIR_PORT_ADD,
RDI_SET_PRIO,
RDI_MIR_VLAN_ADD,
RDI_ADD_VLAN_PROMISC,
RDI_DEL_VLAN_PROMISC,
RDI_GET_PORT_SPEED,
RDI_GET_PORT_ETH_MODE,
RDI_MCG_CREATE,
RDI_MCG_GET_PORT,
RDI_MCG_ADD_LISTENER,
RDI_MCG_REMOVE,
RDI_SET_PORT_PARSER,
RDI_GET_PORT_PARSER,
RDI_SET_RFRAME_UPDATE,
RDI_GET_RFRAME_UPDATE,
RDI_SET_TTL_UPDATE,
RDI_GET_TTL_UPDATE,
RDI_SET_SW_REMAIN,
RDI_GET_SW_REMAIN,
RDI_READ_PHY=100,
RDI_WRITE_PHY,
RDI_CPLD_READ,
@ -57,10 +85,28 @@ enum rdi_conf {
RDI_SET_GPIO,
RDI_GET_REG,
RDI_SET_REG,
RDI_TEMP_READ,
RDI_TEMP_WRITE,
RDI_SET_PRBS,
RDI_GET_PORT_STATE,
RDI_SET_LOOPBACK,
RDI_TEMP1_READ,
RDI_TEMP1_WRITE,
RDI_FCI_READ,
RDI_FCI_WRITE,
RDI_FCI_RX_READ,
RDI_FCI_RX_WRITE,
RDI_GET_VLAN_STAT=200,
RDI_GET_STAT,
RDI_GET_PRIO_STAT,
RDI_RESET_STAT,
RDI_GET_POWER,
} ;
@ -69,7 +115,7 @@ enum rdi_action {
RDI_ACT_PERMIT=0,
RDI_ACT_DROP=1,
RDI_ACT_TRAP, //2
RDI_ACI_MIRROR, //3
RDI_ACT_MIRROR, //3
RDI_ACT_LOG, //4
RDI_ACT_COUNT, //5
RDI_ACT_NOTIFY, //6
@ -130,13 +176,12 @@ typedef struct rdi_mem {
int vlan_mask;
int vlan_max;
int mirror_port;
int mpls_type;
int mpls_label;
short mpls_exp_bits;
short mpls_s_bit;
int mpls_label_mask;
short mpls_exp_bits_mask;
short mpls_s_bit_mask;
uint64_t mpls_header;
uint64_t mpls_header_mask;
int ether_type;
rdi_udf_t rdi_udf;
rdi_mac_t src_mac;
@ -159,7 +204,7 @@ typedef struct rdi_query_rule {
typedef struct rdi_id_list {
unsigned int rule_num;
unsigned char id_list[2048];
unsigned short id_list[4096];
} rdi_id_list_t;
@ -288,6 +333,11 @@ typedef struct rdif_stat_cnt {
unsigned long long cntStatsDropCountRx;
} rdif_stat_cnt_t;
typedef struct rdif_prio_stat_cnt {
unsigned long long cntRxPriorityPkts[16];
} rdif_prio_stat_cnt_t;
typedef struct _rdi_hashRotationValue {
/** The shift amount in the operation is one plus this value. */
unsigned char exponent;
@ -549,6 +599,7 @@ typedef struct rdi_l3_hash {
typedef union rdi_stat_cnt {
rdib_stat_cnt_t rdib;
rdif_stat_cnt_t rdif;
rdif_prio_stat_cnt_t prio_rdif;
}rdi_stat_cnt_t;
@ -623,7 +674,7 @@ typedef struct if_rdi {
typedef struct rdi_lbg_list {
int num;
int list[16];
int list[32];
} rdi_lbg_list_t;
@ -645,7 +696,7 @@ typedef struct if_rdi_lbg {
typedef struct rdi_bp_data_list {
unsigned int num;
unsigned char list[2048];
unsigned char list[4096];
} rdi_bp_data_t;
typedef struct rdi_bp_query_data {
@ -671,7 +722,146 @@ typedef struct if_rdi_mask {
unsigned int rdi_cmd;
unsigned int unit;
rdi_mask_t mask;
} if_rdi_mask_t;
} if_rdi_mask_t;
#define RDI_ETH_MODE_ENABLED_BIT_MASK 0x010000
#define RDI_ETH_MODE_4_LANE_BIT_MASK 0x020000
#define RDI_ETH_MODE_40G_BIT_MASK 0x040000
#define RDI_ETH_MODE_100G_BIT_MASK 0x080000
#define RDI_ETH_MODE_LR_BIT_MASK 0x100000
#define RDI_ETH_MODE_MULTI_LANE_MASK ( RDI_ETH_MODE_4_LANE_BIT_MASK )
enum rdi_eth_mode
{
/** Port is disabled on the specified MAC. No lanes will be used.
* A port must be put in this state when another port sharing the
* same MAC is using a 4-lane mode. This is the default value
* for the ''RDI_PORT_ETHERNET_INTERFACE_MODE'' attribute. */
RDI_ETH_MODE_DISABLED = 0,
/**************************************************
* Non-40G, 1-lane modes
**************************************************/
/** SGMII: 1G, 1 lane, 8b/10b encoding. */
RDI_ETH_MODE_SGMII = RDI_ETH_MODE_ENABLED_BIT_MASK,
/** 1000BASE-X: 1G, 1 lane, 8b/10b encoding. */
RDI_ETH_MODE_1000BASE_X,
/** 1000BASE-KX: 1G, 1 lane, 8b/10b encoding. */
RDI_ETH_MODE_1000BASE_KX,
/** 2500BASE-X: 1G, 1 lane, 8b/10b encoding.
* This is experimental and to be used for internal purposes only. */
RDI_ETH_MODE_2500BASE_X,
/** 6GBASE-KR: 6G, 1 lane, 64b/66b encoding.
* This is experimental and to be used for internal purposes only. */
RDI_ETH_MODE_6GBASE_KR,
/** 6GBASE-CR: 6G, 1 lane, 64b/66b encoding.
* This is experimental and to be used for internal purposes only. */
RDI_ETH_MODE_6GBASE_CR,
/** 10GBASE-KR: 10G, 1 lane, 64b/66b encoding.
* This mode is read-only, i.e., it can be set only through Clause-73
* autonegotiation. */
RDI_ETH_MODE_10GBASE_KR,
/** 10GBASE-CR (SFP+): 10G, 1 lane, 64b/66b encoding. */
RDI_ETH_MODE_10GBASE_CR,
/** 10GBASE-SR (SFP+, SFI): 10G, 1 lane, 64b/66b encoding. */
RDI_ETH_MODE_10GBASE_SR,
/** 25GBASE-SR (SFP+, SFI): 25G, 1 lane, 64/66b encoding. */
RDI_ETH_MODE_25GBASE_SR,
/** 25GBASE-KR: 25G, 1 lane, 64/66b encoding.
* This mode is read-only, i.e., it can be set only through Clause-73
* autonegotiation. */
RDI_ETH_MODE_25GBASE_KR
,
/** 25GBASE-CR: 25G, 1 lane, 64/66b encoding.
* This mode is read-only, i.e., it can be set only through Clause-73
* autonegotiation. */
RDI_ETH_MODE_25GBASE_CR,
/** AN-73: Auto-negotiation Clause 73. */
RDI_ETH_MODE_AN_73,
/**************************************************
* Non-40G, 4-lane modes
**************************************************/
/** XAUI: 10G, 4 lanes, 8b/10b encoding.
* \lb\lb
* Note: After configuring this mode on the second port (P1) of the
* set of four ports sharing a MAC, before setting the port to another
* mode, you must first set the mode to ''RDI_ETH_MODE_DISABLED''. */
RDI_ETH_MODE_XAUI = (RDI_ETH_MODE_4_LANE_BIT_MASK |
RDI_ETH_MODE_ENABLED_BIT_MASK),
/** 10GBASE-KX4: 10G, 4 lanes, 8b/10b encoding. */
RDI_ETH_MODE_10GBASE_KX4,
/** 10GBASE-CX4: 10G, 4 lanes, 8b/10b encoding. */
RDI_ETH_MODE_10GBASE_CX4,
/**************************************************
* 40G, 4-lane modes (treat 24GBASE as 40G)
**************************************************/
/** 24GBASE-KR4: 24G, 4 lanes, 64b/66b encoding.
* This is experimental and to be used for internal purposes only. */
RDI_ETH_MODE_24GBASE_KR4 = (RDI_ETH_MODE_40G_BIT_MASK |
RDI_ETH_MODE_4_LANE_BIT_MASK |
RDI_ETH_MODE_ENABLED_BIT_MASK),
/** 24GBASE-CR4: 24G, 4 lanes, 64b/66b encoding.
* This is experimental and to be used for internal purposes only. */
RDI_ETH_MODE_24GBASE_CR4,
/** 40GBASE-KR4: 40G, 4 lane, 64b/66b encoding.
* This mode is read-only, i.e., it can be set only through Clause-73
* autonegotiation. */
RDI_ETH_MODE_40GBASE_KR4,
/** XLAUI: 40G, 4 lane, 64b/66b encoding. */
RDI_ETH_MODE_XLAUI,
/** 40GBASE-CR4 (QSFP 5M Direct Attach): 40G, 4 lane, 64b/66b encoding.
* This mode is read-only, i.e., it can be set only through Clause-73
* autonegotiation. */
RDI_ETH_MODE_40GBASE_CR4,
/** 40GBASE-SR4 (QSFP PMD Service Interface): 40G, 4 lane, 64b/66b
* encoding. */
RDI_ETH_MODE_40GBASE_SR4,
/** 100GBASE-SR4 (QSFP PMD Service Interface): 100G, 4 lane, 64b/66b
* encoding. */
RDI_ETH_MODE_100GBASE_SR4 = ( RDI_ETH_MODE_100G_BIT_MASK |
RDI_ETH_MODE_4_LANE_BIT_MASK |
RDI_ETH_MODE_ENABLED_BIT_MASK ),
/** 40GBASE-CR4: 100G, 4 lanes, 64b/66b encoding. This mode is read-only,
* i.e., it can be set only through Clause-73 autonegotiation. */
RDI_ETH_MODE_100GBASE_CR4,
/** 40GBASE-KR4: 100G, 4 lanes, 64b/66b encoding. This mode is read-only,
* i.e., it can be set only through Clause-73 autonegotiation. */
RDI_ETH_MODE_100GBASE_KR4,
RDI_ETH_MODE_40GBASE_LR4 = (RDI_ETH_MODE_40GBASE_SR4 | RDI_ETH_MODE_LR_BIT_MASK),
RDI_ETH_MODE_100GBASE_LR4 = (RDI_ETH_MODE_100GBASE_SR4 | RDI_ETH_MODE_LR_BIT_MASK),
};
@ -705,6 +895,8 @@ int rdi_get_rule_counters(int unit, int rule_id, int group, void *val, rdi_type_
int rdi_entry_query_list(int unit, int group, rdi_query_list_t *rdi_query_list, rdi_type_t rdi_type);
int rdi_get_vlan_stat(int unit, int port, rdi_vlan_stat_cnt_t *rdi_vlan_stat_cnt, rdi_type_t rdi_type);
int rdi_get_stat(int unit, int port, rdi_stat_cnt_t *val, rdi_type_t rdi_type);
int rdi_get_prio_stat(int unit, int port, rdi_stat_cnt_t *val, rdi_type_t rdi_type);
int rdi_reset_stat(int unit, int port, rdi_type_t rdi_type);
int rdi_get_rule_stat(int unit, int rule_id, int group, rdi_rule_stat_cnt_t *rdi_rule_stat_cnt, rdi_type_t rdi_type);
int rdi_read_phy(int unit, int phy_addr, int dev, int addr, rdi_type_t rdi_type);
int rdi_write_phy(int unit, int phy_addr, int dev, int addr, int val, rdi_type_t rdi_type);
@ -712,9 +904,15 @@ int rdi_write_phy(int unit, int phy_addr, int dev, int addr, int val, rdi_type_t
int rdi_get_gpio_dir(int unit, int gpio, rdi_type_t rdi_type);
int rdi_set_gpio_dir(int unit, int gpio, int dir, int val, rdi_type_t rdi_type);
int rdi_set_prbs(int unit, int prbs, int dir, int port, rdi_type_t rdi_type);
int rdi_get_gpio(int unit, int gpio, rdi_type_t rdi_type);
int rdi_set_gpio(int unit, int gpio, int val, rdi_type_t rdi_type);
int rdi_set_loopback(int unit, int val, int port, rdi_type_t rdi_type);
int rdi_get_reg(int unit, unsigned int addr, unsigned int *val, rdi_type_t rdi_type);
int rdi_set_reg(int unit, unsigned int addr, unsigned int val, rdi_type_t rdi_type);
@ -742,15 +940,63 @@ int rdi_get_l3_hash(int unit, rdi_l3_hash_t *l3_hash, rdi_type_t rdi_type);
int rdi_lbg_query_entry_list(int unit, struct rdi_lbg_query_list *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_lbg_port_query_entry_list(int unit, int lbg, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_lbg_remove(int unit, int lbg, rdi_type_t rdi_type);
int rdi_lbg_add(int unit, int *lbg, rdi_type_t rdi_type);
int rdi_lbg_add_fn(int unit, int *lbg, rdi_lbg_list_t *rdi_lbg_list, rdi_type_t rdi_type);
int rdi_lbg_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_lbg_port_add(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_mir_query_entry_list(int unit, struct rdi_lbg_query_list *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_mir_port_query_entry_list(int unit, int lbg, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type);
int rdi_mir_remove(int unit, int lbg, rdi_type_t rdi_type);
int rdi_mir_add_fn(int unit, int lbg, rdi_lbg_list_t *rdi_lbg_list, rdi_type_t rdi_type);
int rdi_mir_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_mir_port_add(int unit, int lbg, int port, rdi_type_t rdi_type);
int rdi_mir_vlan_add(int unit, int lbg, int vlan_id, rdi_type_t rdi_type);
int rdi_add_vlan_promisc(int unit, int port, rdi_type_t rdi_type);
int rdi_del_vlan_promisc(int unit, int port, rdi_type_t rdi_type);
int rdi_mcg_create(int unit, rdi_type_t rdi_type);
int rdi_mcg_get_port(int unit, int mcg, rdi_type_t rdi_type);
int rdi_mcg_add_listener(int unit, int mcg, int port, int vlan, rdi_type_t type);
int rdi_mcg_remove(int unit, int mcg, rdi_type_t rdi_type);
int rdi_get_rframe_update(int unit, int port, rdi_type_t rdi_type);
int rdi_set_rframe_update(int unit, int port, int val, rdi_type_t rdi_type);
int rdi_get_ttl_update(int unit, int port, rdi_type_t rdi_type);
int rdi_set_ttl_update(int unit, int port, int val, rdi_type_t rdi_type);
int rdi_get_port_parser(int unit, int port, rdi_type_t rdi_type);
int rdi_set_port_parser(int unit, int port, int val, rdi_type_t rdi_type);
int rdi_get_port_link(int unit, int port, rdi_type_t rdi_type);
int rdi_get_port_speed(int unit, int port, rdi_type_t rdi_type);
int rdi_get_eth_mode(int unit, int port, rdi_type_t rdi_type);
int rdi_get_port_state(int unit, int port, int *mode, int *state, int *info, rdi_type_t rdi_type);
int rdi_bp_read(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_bp_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_fci_read(int unit, int fci_num, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data,
rdi_type_t rdi_type);
int rdi_fci_write(int unit, int fci_num, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data,
rdi_type_t rdi_type);
int rdi_fci_rx_read(int unit, int fci_num, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data,
rdi_type_t rdi_type);
int rdi_fci_rx_write(int unit, int fci_num, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data,
rdi_type_t rdi_type);
int rdi_temp_read(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_temp_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_temp1_read(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_temp1_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type);
int rdi_get_sw_remain(rdi_type_t rdi_type);
int rdi_set_sw_remain(int val, rdi_type_t rdi_type);
#endif /* _RDD_LIB_H_ */

View File

@ -12,6 +12,7 @@
/* librdi.c */
/* */
/******************************************************************************/
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <errno.h>
@ -20,6 +21,20 @@
#include <sys/socket.h>
#include <sys/un.h>
#include <unistd.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <ctype.h>
#include <byteswap.h>
#include <time.h>
#include <sys/syslog.h>
#include <signal.h>
#include <net/if.h>
#include <sys/socket.h>
#include "../include/librdi.h"
@ -165,6 +180,7 @@ static int send_cmd_query_list(if_rdi_t *if_rdi, struct rdi_query_list *rdi_quer
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
@ -181,6 +197,45 @@ static int send_cmd_query_list(if_rdi_t *if_rdi, struct rdi_query_list *rdi_quer
}
static int send_cmd_query_data(if_rdi_t *if_rdi, rdi_bp_query_data_t *rdi_query_list,rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {
perror("librdi socket");
return -1;
}
remote.sun_family = AF_UNIX;
if (rdi_type==RDI_FLCM_DEV)
strcpy(remote.sun_path, RDIF_SOCK_PATH);
else
strcpy(remote.sun_path, RDI_SOCK_PATH);
len = strlen(remote.sun_path) + sizeof(remote.sun_family);
if (connect(s, (struct sockaddr *)&remote, len) == -1) {
perror("librdi connect");
close(s);
return -1;
}
if (send(s, if_rdi, sizeof(if_rdi_t), 0) == -1) {
perror("librdi send");
close(s);
return -1;
}
if ((t=recv(s, rdi_query_list, sizeof(rdi_bp_query_data_t), 0)) < 0) {
perror("librdi recv");
close(s);
return -1;
}
close(s);
return 0;
}
static int send_cmd_lbg_query_list(if_rdi_t *if_rdi, struct rdi_lbg_query_list *rdi_lbg_query_list,rdi_type_t rdi_type){
int s, t, len;
struct sockaddr_un remote;
@ -255,17 +310,35 @@ int rdi_get_cfg(int unit, rdi_type_t rdi_type){
}
int rdi_get_temp(int unit, rdi_type_t rdi_type){
int ret=0;
unsigned int val;
unsigned int subdevice;
unsigned int dev_addr=0;
rdi_bp_query_data_t rdi_bp_query_data;
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
return -1;
if_rdi.rdi_cmd=RDI_GET_TEMP;
if_rdi.unit=unit;
memset(&rdi_bp_query_data, 0, sizeof(rdi_bp_query_data_t));
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
if ((ret = rdi_get_reg(unit, 0x12000b, (unsigned int *)&val, RDI_FLCM_DEV))<0) {
return -1;
}
subdevice = (val >> 16) & 0xffff;
if(((subdevice & 0xff0) == 0x01B0) ||
(subdevice == 0))
dev_addr = 0x2c;
else
dev_addr = 0x2e;
if (!rdi_type)
rdi_type=RDI_FLCM_DEV;
rdi_bp_query_data.data.num = 1;
if ((rdi_temp_read(unit, dev_addr, &rdi_bp_query_data, rdi_type))<0)
return -1;
else
return rdi_bp_query_data.data.list[0];
}
@ -286,6 +359,71 @@ int rdi_get_port_link(int unit, int port, rdi_type_t rdi_type){
}
int rdi_get_port_speed(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_PORT_SPEED;
if_rdi.unit=unit;
if_rdi.port=port;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_get_eth_mode(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_GET_PORT_ETH_MODE;
if_rdi.unit=unit;
if_rdi.port=port;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_add_vlan_promisc(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_ADD_VLAN_PROMISC;
if_rdi.unit=unit;
if_rdi.port=port;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_del_vlan_promisc(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_DEL_VLAN_PROMISC;
if_rdi.unit=unit;
if_rdi.port=port;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret) , rdi_type)))
return ret;
return -1;
}
int rdi_install_rules(int unit, rdi_type_t rdi_type){
@ -512,6 +650,53 @@ int rdi_lbg_query_entry_list(int unit, rdi_lbg_query_list_t *rdi_lbg_query_list,
}
int rdi_mir_query_entry_list(int unit, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type){
if_rdi_t if_rdi;
if_rdi_lbg_t *if_rdi_lbg;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi_lbg=(if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd=RDI_MIR_QUERY_LIST;
if_rdi_lbg->unit=unit;
if (!rdi_lbg_query_list)
return -1;
if (!(send_cmd_lbg_query_list(&if_rdi, rdi_lbg_query_list, rdi_type))) {
return rdi_lbg_query_list->ret;
} else return -1;
}
int rdi_get_port_state(int unit, int port, int *mode, int *state, int *info, rdi_type_t rdi_type){
if_rdi_t if_rdi;
if_rdi_lbg_t *if_rdi_lbg;
rdi_lbg_query_list_t rdi_lbg_query_list;
memset(&if_rdi,0,sizeof(if_rdi_t));
memset(&rdi_lbg_query_list,0,sizeof(rdi_lbg_query_list_t));
if_rdi_lbg = (if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd = RDI_GET_PORT_STATE;
if_rdi_lbg->unit = unit;
if_rdi_lbg->lbg = port;
if (!(send_cmd_lbg_query_list(&if_rdi, &rdi_lbg_query_list, rdi_type))) {
*mode = rdi_lbg_query_list.rdi_lbg_list.list[0];
*state = rdi_lbg_query_list.rdi_lbg_list.list[1];
*info = rdi_lbg_query_list.rdi_lbg_list.list[2];
*(info+1) = rdi_lbg_query_list.rdi_lbg_list.list[3];
*(info+2) = rdi_lbg_query_list.rdi_lbg_list.list[4];
*(info+3) = rdi_lbg_query_list.rdi_lbg_list.list[5];
return rdi_lbg_query_list.ret;
} else return -1;
}
int rdi_bp_read(int unit, int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
@ -530,7 +715,7 @@ int rdi_bp_read(int unit, int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_t
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_list(&if_rdi, (struct rdi_query_list *) rdi_bp_query_data, rdi_type))) {
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
@ -551,13 +736,188 @@ int rdi_bp_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_t
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_list(&if_rdi, (struct rdi_query_list *) rdi_bp_query_data, rdi_type))) {
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_fci_read(int unit, int dev, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_FCI_READ;
if_rdi.unit = unit;
if_rdi.phy_addr = dev;
if_rdi.addr = offset;
if_rdi.dev = page;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_fci_write(int unit, int dev, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_FCI_WRITE;
if_rdi.unit = unit;
if_rdi.phy_addr = dev;
if_rdi.addr = offset;
if_rdi.dev = page;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_fci_rx_read(int unit, int dev, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_FCI_RX_READ;
if_rdi.unit = unit;
if_rdi.phy_addr = dev;
if_rdi.addr = offset;
if_rdi.dev = page;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_fci_rx_write(int unit, int dev, int offset, int page, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_FCI_RX_WRITE;
if_rdi.unit = unit;
if_rdi.phy_addr = dev;
if_rdi.addr = offset;
if_rdi.dev = page;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_temp_read(int unit, int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_TEMP_READ;
if_rdi.unit=unit;
if_rdi.dev=dev;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type)))
return rdi_bp_query_data->ret;
else
return -1;
}
int rdi_temp_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_TEMP_WRITE;
if_rdi.unit=unit;
if_rdi.dev=dev;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_temp1_read(int unit, int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_TEMP1_READ;
if_rdi.unit=unit;
if_rdi.dev=dev;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type)))
return rdi_bp_query_data->ret;
else
return -1;
}
int rdi_temp1_write(int unit,int dev, rdi_bp_query_data_t *rdi_bp_query_data, rdi_type_t rdi_type){
if_rdi_t if_rdi;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_TEMP1_WRITE;
if_rdi.unit=unit;
if_rdi.dev=dev;
if (!rdi_bp_query_data)
return -1;
memcpy(&if_rdi.rdi_query_list, rdi_bp_query_data, sizeof(rdi_bp_query_data_t));
if (!(send_cmd_query_data(&if_rdi, rdi_bp_query_data, rdi_type))) {
return rdi_bp_query_data->ret;
} else return -1;
}
int rdi_lbg_port_query_entry_list(int unit, int lbg, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type){
if_rdi_t if_rdi;
if_rdi_lbg_t *if_rdi_lbg;
@ -589,32 +949,34 @@ int rdi_lbg_remove(int unit, int lbg, rdi_type_t rdi_type){
if_rdi_lbg=(if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd=RDI_LBG_REMOVE;
if_rdi_lbg->lbg=lbg;
if_rdi_lbg->unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_lbg_add_fn(int unit, int *lbg, rdi_lbg_list_t *rdi_lbg_list, rdi_type_t rdi_type)
{
int ret=0;
if_rdi_lbg_t if_rdi_lbg;
if_rdi_t *if_rdi = (if_rdi_t *)&if_rdi_lbg;
memset(&if_rdi_lbg, 0, sizeof(if_rdi_lbg_t));
int rdi_lbg_add(int unit, int *lbg, rdi_type_t rdi_type){
if_rdi_lbg.rdi_cmd = RDI_LBG_ADD;
if_rdi_lbg.unit = unit;
memcpy(&if_rdi_lbg.rdi_query_list.rdi_lbg_list, rdi_lbg_list, sizeof(rdi_lbg_list_t));
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_LBG_ADD;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type))) {
if (ret<=0)
if (!(send_cmd(if_rdi, &ret, sizeof(ret), rdi_type))) {
if (ret < 0)
return -1;
*lbg= ret;
*lbg = ret;
return 0;
} else return -1;
}
int rdi_lbg_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type){
@ -626,6 +988,7 @@ int rdi_lbg_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type){
if_rdi.rdi_cmd=RDI_LBG_PORT_REMOVE;
if_rdi_lbg->lbg=lbg;
if_rdi_lbg->port=port;
if_rdi_lbg->unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
@ -645,6 +1008,7 @@ int rdi_lbg_port_add(int unit, int lbg, int port, rdi_type_t rdi_type){
if_rdi.rdi_cmd=RDI_LBG_PORT_ADD;
if_rdi_lbg->lbg=lbg;
if_rdi_lbg->port=port;
if_rdi_lbg->unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type))) {
return ret;
@ -652,9 +1016,307 @@ int rdi_lbg_port_add(int unit, int lbg, int port, rdi_type_t rdi_type){
}
int rdi_mir_port_query_entry_list(int unit, int lbg, rdi_lbg_query_list_t *rdi_lbg_query_list, rdi_type_t rdi_type){
if_rdi_t if_rdi;
if_rdi_lbg_t *if_rdi_lbg;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi_lbg=(if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd = RDI_MIR_PORT_QUERY_LIST;
if_rdi_lbg->unit = unit;
if_rdi_lbg->lbg = lbg;
if (!rdi_lbg_query_list)
return -1;
if (!(send_cmd_lbg_query_list(&if_rdi, rdi_lbg_query_list, rdi_type))) {
return rdi_lbg_query_list->ret;
} else return -1;
}
int rdi_mir_remove(int unit, int lbg, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
if_rdi_lbg_t *if_rdi_lbg;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi_lbg = (if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd = RDI_MIR_REMOVE;
if_rdi_lbg->lbg = lbg;
if_rdi_lbg->unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_mir_add_fn(int unit, int lbg, rdi_lbg_list_t *rdi_lbg_list, rdi_type_t rdi_type)
{
int ret=0;
if_rdi_lbg_t if_rdi_lbg;
if_rdi_t *if_rdi = (if_rdi_t *)&if_rdi_lbg;
memset(&if_rdi_lbg, 0, sizeof(if_rdi_lbg_t));
if_rdi_lbg.rdi_cmd = RDI_MIR_ADD;
if_rdi_lbg.unit = unit;
if_rdi_lbg.lbg = lbg;
memcpy(&if_rdi_lbg.rdi_query_list.rdi_lbg_list, rdi_lbg_list, sizeof(rdi_lbg_list_t));
if (!(send_cmd(if_rdi, &ret, sizeof(ret), rdi_type))) {
if (ret < 0)
return -1;
return 0;
} else return -1;
}
int rdi_mir_port_remove(int unit, int lbg, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
if_rdi_lbg_t *if_rdi_lbg;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi_lbg=(if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd=RDI_MIR_PORT_REMOVE;
if_rdi_lbg->lbg=lbg;
if_rdi_lbg->port=port;
if_rdi_lbg->unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_mir_port_add(int unit, int lbg, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
if_rdi_lbg_t *if_rdi_lbg;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi_lbg=(if_rdi_lbg_t *)&if_rdi;
if_rdi.rdi_cmd=RDI_MIR_PORT_ADD;
if_rdi_lbg->lbg=lbg;
if_rdi_lbg->port=port;
if_rdi_lbg->unit=unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type))) {
return ret;
} else return -1;
}
int rdi_mir_vlan_add(int unit, int lbg, int vlan, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret=0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd=RDI_MIR_VLAN_ADD;
if_rdi.unit=unit;
if_rdi.port=lbg;
if_rdi.group=vlan;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type))) {
return ret;
} else return -1;
}
int rdi_mcg_create(int unit, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_MCG_CREATE;
if_rdi.unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_mcg_get_port(int unit, int mcg, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_MCG_GET_PORT;
if_rdi.group = mcg;
if_rdi.unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_mcg_add_listener(int unit, int mcg, int port, int vlan, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_MCG_ADD_LISTENER;
if_rdi.group = mcg;
if_rdi.port = port;
if_rdi.val = vlan;
if_rdi.unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_mcg_remove(int unit, int mcg, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_MIR_REMOVE;
if_rdi.group = mcg;
if_rdi.unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_set_port_parser(int unit, int port, int val, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_SET_PORT_PARSER;
if_rdi.port = port;
if_rdi.val = val;
if_rdi.unit = unit;
if (!(send_cmd(&if_rdi, &ret, sizeof(ret), rdi_type)))
return ret;
else return -1;
}
int rdi_get_port_parser(int unit, int port, rdi_type_t rdi_type){
if_rdi_t if_rdi;
int ret = 0;
memset(&if_rdi,0,sizeof(if_rdi_t));
if_rdi.rdi_cmd = RDI_GET_PORT_PARSER;
if_rdi.port = port;
if_rdi.unit = unit;