Add further config values, set spi values for rrcc to use
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@ -5,7 +5,7 @@ Experimental project for replacing factory firmware on FM10000 cards with custom
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WARNING: **This is a Work In Progress project**. Do not use on any cards you don't want to have to unbrick via manual SPI connection.
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### Requirements
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* [rrcc](https://git.gammaspectra.live/FM10K/rrcc) (will build it from submodule)
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* [rrcc](https://git.gammaspectra.live/FM10K/rrcc) (will be built from submodule, tagged to specific version. Make sure to do `$ git submodule update --init --recursive` before building)
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* make
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### Compilation
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88
config.asm
88
config.asm
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@ -1,10 +1,16 @@
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; File used to declare configuration to be placed on the firmware image
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; Defaults to values found on Silicom PE3100G2DQiRM-QX4 card, as an example
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.constant platform_firmware_versionNumber 0x0222 ; Define version reported back on register. 0x0222 = same as rrcBig_02.22
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.constant bootCfg_spiTransferMode 0
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.constant bootCfg_spiTransferSpeed 7
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; Picks between DEVICE_CFG.SystimeClockSource values. 0 = PCIE_REFCLK, 1 = IEEE1588_REFCLK
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.constant bootCfg_systimeClockSource 0
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.constant bootCfg_enableSwitchRdySignal 0
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.constant bootCfg_skipMemRepair 0
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.constant bootCfg_skipPcieInitialization 0
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@ -24,6 +30,88 @@
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.constant bootCfg_pep4_mode 0
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.constant bootCfg_pep6_mode 0
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.constant bootCfg_pep0_numberOfLanes 8
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.constant bootCfg_pep1_numberOfLanes 0
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.constant bootCfg_pep2_numberOfLanes 8
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.constant bootCfg_pep3_numberOfLanes 0
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.constant bootCfg_pep4_numberOfLanes 8
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.constant bootCfg_pep5_numberOfLanes 0
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.constant bootCfg_pep6_numberOfLanes 8
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.constant bootCfg_pep7_numberOfLanes 0
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.constant bootCfg_pep8_numberOfLanes 0
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.constant bootCfg_pep0_gen 3
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.constant bootCfg_pep1_gen 3
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.constant bootCfg_pep2_gen 3
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.constant bootCfg_pep3_gen 3
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.constant bootCfg_pep4_gen 3
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.constant bootCfg_pep5_gen 3
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.constant bootCfg_pep6_gen 3
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.constant bootCfg_pep7_gen 3
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.constant bootCfg_pep8_gen 3
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.constant bootCfg_pep0_bar4Allowed 1
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.constant bootCfg_pep1_bar4Allowed 0
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.constant bootCfg_pep2_bar4Allowed 1
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.constant bootCfg_pep3_bar4Allowed 0
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.constant bootCfg_pep4_bar4Allowed 1
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.constant bootCfg_pep5_bar4Allowed 0
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.constant bootCfg_pep6_bar4Allowed 1
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.constant bootCfg_pep7_bar4Allowed 0
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.constant bootCfg_pep8_bar4Allowed 0
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.constant bootCfg_pep0_ASPMEnable 0
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.constant bootCfg_pep1_ASPMEnable 0
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.constant bootCfg_pep2_ASPMEnable 0
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.constant bootCfg_pep3_ASPMEnable 0
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.constant bootCfg_pep4_ASPMEnable 0
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.constant bootCfg_pep5_ASPMEnable 0
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.constant bootCfg_pep6_ASPMEnable 0
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.constant bootCfg_pep7_ASPMEnable 0
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.constant bootCfg_pep8_ASPMEnable 0
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.constant bootCfg_pep0_vendorId 0x8086 ; Intel Corporation
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.constant bootCfg_pep1_vendorId 0x8086
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.constant bootCfg_pep2_vendorId 0x8086
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.constant bootCfg_pep3_vendorId 0x8086
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.constant bootCfg_pep4_vendorId 0x8086
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.constant bootCfg_pep5_vendorId 0x8086
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.constant bootCfg_pep6_vendorId 0x8086
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.constant bootCfg_pep7_vendorId 0x8086
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.constant bootCfg_pep8_vendorId 0x8086
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.constant bootCfg_pep0_deviceId 0x15A4 ; Ethernet Switch FM10000 Host Interface
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.constant bootCfg_pep1_deviceId 0x15A4
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.constant bootCfg_pep2_deviceId 0x15A4
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.constant bootCfg_pep3_deviceId 0x15A4
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.constant bootCfg_pep4_deviceId 0x15A4
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.constant bootCfg_pep5_deviceId 0x15A4
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.constant bootCfg_pep6_deviceId 0x15A4
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.constant bootCfg_pep7_deviceId 0x15A4
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.constant bootCfg_pep8_deviceId 0x15A4
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.constant bootCfg_pep0_subVendorId 0x1374
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.constant bootCfg_pep1_subVendorId 0x1374
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.constant bootCfg_pep2_subVendorId 0x1374
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.constant bootCfg_pep3_subVendorId 0x1374
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.constant bootCfg_pep4_subVendorId 0x1374
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.constant bootCfg_pep5_subVendorId 0x1374
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.constant bootCfg_pep6_subVendorId 0x1374
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.constant bootCfg_pep7_subVendorId 0x1374
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.constant bootCfg_pep8_subVendorId 0x1374
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.constant bootCfg_pep0_subDeviceId 0x01C2
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.constant bootCfg_pep1_subDeviceId 0
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.constant bootCfg_pep2_subDeviceId 0x01C2
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.constant bootCfg_pep3_subDeviceId 0
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.constant bootCfg_pep4_subDeviceId 0x01C2
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.constant bootCfg_pep5_subDeviceId 0
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.constant bootCfg_pep6_subDeviceId 0x01C2
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.constant bootCfg_pep7_subDeviceId 0
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.constant bootCfg_pep8_subDeviceId 0
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; Custom macs are composed of two 32-bit values, reversed
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.constant bootCfg_customMac0 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
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.constant bootCfg_customMac1 0xff000000, 0x000000ff ; Corresponds to 00:00:00:FF:FF:00:00:00
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2
rrcc
2
rrcc
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@ -1 +1 @@
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Subproject commit 1566c33d5840c88df5ccb591849cda8965ddf628
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Subproject commit e76befaed778735115a0faa1559511368ba7b350
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@ -23,6 +23,9 @@
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.constant rrcc_SPI_TRANSFER_MODE, bootCfg_spiTransferMode
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.constant rrcc_SPI_TRANSFER_SPEED, bootCfg_spiTransferSpeed
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.constant rrcc_IMAGE_VERSION, platform_firmware_versionNumber
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entrypoint:
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CALL @init_startClocks
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